commit 6dd29e08f7d4e0c0f10086ca8b315d9b51a77a45
author Bill Wendling <isanbard@gmail.com> Tue Apr 24 21:17:46 2007 +0000
committer Bill Wendling <isanbard@gmail.com> Tue Apr 24 21:17:46 2007 +0000
tree f3c275356ade87d4426817609afc50dcbc034e08
parent 2f9bb1a0a47622d959ec0cee25a7346c55066817

Remove some invalid instructions from this check.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36404 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86InstrInfo.cpp

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index d58c49e..7a3dfe0 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -38,8 +38,7 @@
       oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
       oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
       oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
-      oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr ||
-      oc == X86::MMX_MOVDQ2Qrr || oc == X86::MMX_MOVQ2DQrr) {
+      oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) {
       assert(MI.getNumOperands() == 2 &&
              MI.getOperand(0).isRegister() &&
              MI.getOperand(1).isRegister() &&