initial implementation of addressing mode 2
TODO: fix lea_addri
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31552 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 281966b..6945540 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -18,6 +18,11 @@
let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
}
+def op_addr_mode2 : Operand<iPTR> {
+ let PrintMethod = "printAddrMode2";
+ let MIOperandInfo = (ops ptr_rc, i32imm);
+}
+
def op_addr_mode5 : Operand<iPTR> {
let PrintMethod = "printAddrMode5";
let MIOperandInfo = (ops ptr_rc, i32imm);
@@ -33,6 +38,9 @@
def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl],
[]>;
+//Addressing Mode 2: Load and Store Word or Unsigned Byte
+def addr_mode2 : ComplexPattern<iPTR, 2, "SelectAddrMode2", [], []>;
+
//Addressing Mode 5: VFP load/store
def addr_mode5 : ComplexPattern<iPTR, 2, "SelectAddrMode5", [], []>;
@@ -157,9 +165,9 @@
def blx : InstARM<(ops IntRegs:$func, variable_ops), "blx $func", [(ARMcall IntRegs:$func)]>;
}
-def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
+def LDR : InstARM<(ops IntRegs:$dst, op_addr_mode2:$addr),
"ldr $dst, $addr",
- [(set IntRegs:$dst, (load iaddr:$addr))]>;
+ [(set IntRegs:$dst, (load addr_mode2:$addr))]>;
def LDRB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
"ldrb $dst, [$addr]",
@@ -177,9 +185,9 @@
"ldrsh $dst, [$addr]",
[(set IntRegs:$dst, (sextloadi16 IntRegs:$addr))]>;
-def str : InstARM<(ops IntRegs:$src, memri:$addr),
- "str $src, $addr",
- [(store IntRegs:$src, iaddr:$addr)]>;
+def STR : InstARM<(ops IntRegs:$src, op_addr_mode2:$addr),
+ "str $src, $addr",
+ [(store IntRegs:$src, addr_mode2:$addr)]>;
def STRB : InstARM<(ops IntRegs:$src, IntRegs:$addr),
"strb $src, [$addr]",