commit 6ef781f3ce0d0311004adba9d1e7dbd7950918dd
author Bill Wendling <isanbard@gmail.com> Wed Feb 27 06:33:05 2008 +0000
committer Bill Wendling <isanbard@gmail.com> Wed Feb 27 06:33:05 2008 +0000
tree cc00914fa7d90f658540d9f539ce39a742c88e14
parent e1b332a30459a726e882a4f484a9a31f2cea9e29

Final de-tabification.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47663 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
index d8230be..b316d41 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
@@ -134,7 +134,7 @@
     if (G && R->getReg() != 0 &&
         TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
       Op = Op + " " +
-	G->getTarget().getRegisterInfo()->getName(R->getReg());
+        G->getTarget().getRegisterInfo()->getName(R->getReg());
     } else {
       Op += " #" + utostr(R->getReg());
     }

lib/CodeGen/VirtRegMap.cpp

diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 2e2dc5b..d210d93 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -1262,7 +1262,7 @@
           else
             DOUT << "Reusing SS#" << ReuseSlot;
           DOUT << " from physreg " << TRI->getName(PhysReg)
-	       << " for vreg" << VirtReg
+               << " for vreg" << VirtReg
                << " instead of reloading into same physreg.\n";
           unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
           MI.getOperand(i).setReg(RReg);