commit 6f0d024a534af18d9e60b3ea757376cd8a3a980e
author Dan Gohman <gohman@apple.com> Sun Feb 10 18:45:23 2008 +0000
committer Dan Gohman <gohman@apple.com> Sun Feb 10 18:45:23 2008 +0000
tree 24ca65a47eb4948b2fbbc5cfeb1ebfc270bcd45e
parent 6bbba6691e66178a895e3c50cfc553eaf9ace2d0

Rename MRegisterInfo to TargetRegisterInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/RegAllocBigBlock.cpp

diff --git a/lib/CodeGen/RegAllocBigBlock.cpp b/lib/CodeGen/RegAllocBigBlock.cpp
index e6dc744..f2c45ec 100644
--- a/lib/CodeGen/RegAllocBigBlock.cpp
+++ b/lib/CodeGen/RegAllocBigBlock.cpp
@@ -95,7 +95,7 @@
     
     /// RegInfo - For dealing with machine register info (aliases, folds
     /// etc)
-    const MRegisterInfo *RegInfo;
+    const TargetRegisterInfo *RegInfo;
 
     typedef SmallVector<unsigned, 2> VRegTimes;
 
@@ -152,8 +152,8 @@
     /// markVirtRegModified - Lets us flip bits in the VirtRegModified bitset
     ///
     void markVirtRegModified(unsigned Reg, bool Val = true) {
-      assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
-      Reg -= MRegisterInfo::FirstVirtualRegister;
+      assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
+      Reg -= TargetRegisterInfo::FirstVirtualRegister;
       if (VirtRegModified.size() <= Reg)
         VirtRegModified.resize(Reg+1);
       VirtRegModified[Reg] = Val;
@@ -162,10 +162,10 @@
     /// isVirtRegModified - Lets us query the VirtRegModified bitset
     ///
     bool isVirtRegModified(unsigned Reg) const {
-      assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
-      assert(Reg - MRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
+      assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!");
+      assert(Reg - TargetRegisterInfo::FirstVirtualRegister < VirtRegModified.size()
              && "Illegal virtual register!");
-      return VirtRegModified[Reg - MRegisterInfo::FirstVirtualRegister];
+      return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister];
     }
 
   public:
@@ -562,7 +562,7 @@
       MachineOperand& MO = MI->getOperand(i);
       // look for vreg reads..
       if (MO.isRegister() && !MO.isDef() && MO.getReg() &&
-          MRegisterInfo::isVirtualRegister(MO.getReg())) {
+          TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
           // ..and add them to the read table.
           VRegTimes* &Times = VRegReadTable[MO.getReg()];
           if(!VRegReadTable[MO.getReg()]) {
@@ -675,7 +675,7 @@
       MachineOperand& MO = MI->getOperand(i);
       // here we are looking for only used operands (never def&use)
       if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() &&
-          MRegisterInfo::isVirtualRegister(MO.getReg()))
+          TargetRegisterInfo::isVirtualRegister(MO.getReg()))
         MI = reloadVirtReg(MBB, MI, i);
     }
 
@@ -686,7 +686,7 @@
     for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
       unsigned VirtReg = Kills[i];
       unsigned PhysReg = VirtReg;
-      if (MRegisterInfo::isVirtualRegister(VirtReg)) {
+      if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
         // If the virtual register was never materialized into a register, it
         // might not be in the map, but it won't hurt to zero it out anyway.
         unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
@@ -721,7 +721,7 @@
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
       MachineOperand& MO = MI->getOperand(i);
       if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
-          MRegisterInfo::isPhysicalRegister(MO.getReg())) {
+          TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
         unsigned Reg = MO.getReg();
         if (PhysRegsUsed[Reg] == -2) continue;  // Something like ESP.
         // These are extra physical register defs when a sub-register
@@ -777,7 +777,7 @@
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
       MachineOperand& MO = MI->getOperand(i);
       if (MO.isRegister() && MO.isDef() && MO.getReg() &&
-          MRegisterInfo::isVirtualRegister(MO.getReg())) {
+          TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
         unsigned DestVirtReg = MO.getReg();
         unsigned DestPhysReg;
 
@@ -796,7 +796,7 @@
     for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) {
       unsigned VirtReg = DeadDefs[i];
       unsigned PhysReg = VirtReg;
-      if (MRegisterInfo::isVirtualRegister(VirtReg)) {
+      if (TargetRegisterInfo::isVirtualRegister(VirtReg)) {
         unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg);
         PhysReg = PhysRegSlot;
         assert(PhysReg != 0);
@@ -865,7 +865,7 @@
   Virt2PhysRegMap.grow(MF->getRegInfo().getLastVirtReg());
   StackSlotForVirtReg.grow(MF->getRegInfo().getLastVirtReg());
   VirtRegModified.resize(MF->getRegInfo().getLastVirtReg() - 
-                         MRegisterInfo::FirstVirtualRegister + 1, 0);
+                         TargetRegisterInfo::FirstVirtualRegister + 1, 0);
 
   // Loop over all of the basic blocks, eliminating virtual register references
   for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();