diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 3e37417..bd8a54c 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -1296,28 +1296,25 @@
     MachineOperand &O = ri.getOperand();
     ++ri;
     if (MI->isDebugValue()) {
-#if 0
-      // Disabled temporarily.
       // Modify DBG_VALUE now that the value is in a spill slot.
-      uint64_t Offset = MI->getOperand(1).getImm();
-      const MDNode *MDPtr = MI->getOperand(2).getMetadata();
-      DebugLoc DL = MI->getDebugLoc();
-      MachineInstr *NewDV = tii_->emitFrameIndexDebugValue(*mf_, Slot, Offset,
-                                                           MDPtr, DL);
-      if (NewDV) {
-        DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
-        ReplaceMachineInstrInMaps(MI, NewDV);
-        MachineBasicBlock *MBB = MI->getParent();
-        MBB->insert(MBB->erase(MI), NewDV);
-      } else {
-#endif
-        DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI);
-        RemoveMachineInstrFromMaps(MI);
-        vrm.RemoveMachineInstrFromMaps(MI);
-        MI->eraseFromParent();
-#if 0
+      if (Slot == VirtRegMap::NO_STACK_SLOT) {
+        uint64_t Offset = MI->getOperand(1).getImm();
+        const MDNode *MDPtr = MI->getOperand(2).getMetadata();
+        DebugLoc DL = MI->getDebugLoc();
+        if (MachineInstr *NewDV = tii_->emitFrameIndexDebugValue(*mf_, Slot,
+                                                           Offset, MDPtr, DL)) {
+          DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
+          ReplaceMachineInstrInMaps(MI, NewDV);
+          MachineBasicBlock *MBB = MI->getParent();
+          MBB->insert(MBB->erase(MI), NewDV);
+          continue;
+        }
       }
-#endif
+
+      DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI);
+      RemoveMachineInstrFromMaps(MI);
+      vrm.RemoveMachineInstrFromMaps(MI);
+      MI->eraseFromParent();
       continue;
     }
     assert(!O.isImplicit() && "Spilling register that's used as implicit use?");