| commit | 706be918ca917ae38564f0b9940b77ffaf0ddbcf | [log] [tgz] |
|---|---|---|
| author | Andrew Lenharth <andrewl@lenharth.org> | Thu Apr 07 13:55:53 2005 +0000 |
| committer | Andrew Lenharth <andrewl@lenharth.org> | Thu Apr 07 13:55:53 2005 +0000 |
| tree | 3e539c723387cce4dc199d218980083f4b5b5a3d | |
| parent | e6a0b6cbdae12ebb163adffb39d83afb72bb74ef [diff] [blame] |
Yea, it wasn't happy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21132 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index c3b9c1f..6c3a87a 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1136,6 +1136,7 @@ Tmp1 = SelectExpr(N.getOperand(0)); Tmp2 = SelectExpr(N.getOperand(1)); BuildMI(BB, Alpha::UMULH, 2, Result).addReg(Tmp1).addReg(Tmp2); + return Result; case ISD::MULHS: { //MULHU - Ra<63>*Rb - Rb<63>*Ra