commit 7169a2f9e87d3cb13666071b9af022fdb82218e4
author Duncan Sands <baldrick@free.fr> Wed Oct 31 08:57:43 2007 +0000
committer Duncan Sands <baldrick@free.fr> Wed Oct 31 08:57:43 2007 +0000
tree 6b87f8e6c3541c3c13dc7453442dd0e5d7ec1333
parent 1bd3271b16d7f9f0b69af00d8ff29ed00a29f9ef

Promotion of sdiv/srem/udiv/urem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43551 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp
index 5ecda48..2c8044c 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp
@@ -147,6 +147,8 @@
   SDOperand PromoteResult_SETCC(SDNode *N);
   SDOperand PromoteResult_LOAD(LoadSDNode *N);
   SDOperand PromoteResult_SimpleIntBinOp(SDNode *N);
+  SDOperand PromoteResult_SDIV(SDNode *N);
+  SDOperand PromoteResult_UDIV(SDNode *N);
   SDOperand PromoteResult_SHL(SDNode *N);
   SDOperand PromoteResult_SRA(SDNode *N);
   SDOperand PromoteResult_SRL(SDNode *N);
@@ -554,6 +556,12 @@
   case ISD::SUB:
   case ISD::MUL:      Result = PromoteResult_SimpleIntBinOp(N); break;
 
+  case ISD::SDIV:
+  case ISD::SREM:     Result = PromoteResult_SDIV(N); break;
+
+  case ISD::UDIV:
+  case ISD::UREM:     Result = PromoteResult_UDIV(N); break;
+
   case ISD::SHL:      Result = PromoteResult_SHL(N); break;
   case ISD::SRA:      Result = PromoteResult_SRA(N); break;
   case ISD::SRL:      Result = PromoteResult_SRL(N); break;
@@ -694,6 +702,30 @@
   return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
 }
 
+SDOperand DAGTypeLegalizer::PromoteResult_SDIV(SDNode *N) {
+  // Sign extend the input.
+  SDOperand LHS = GetPromotedOp(N->getOperand(0));
+  SDOperand RHS = GetPromotedOp(N->getOperand(1));
+  MVT::ValueType VT = N->getValueType(0);
+  LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
+                    DAG.getValueType(VT));
+  RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
+                    DAG.getValueType(VT));
+
+  return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
+}
+
+SDOperand DAGTypeLegalizer::PromoteResult_UDIV(SDNode *N) {
+  // Zero extend the input.
+  SDOperand LHS = GetPromotedOp(N->getOperand(0));
+  SDOperand RHS = GetPromotedOp(N->getOperand(1));
+  MVT::ValueType VT = N->getValueType(0);
+  LHS = DAG.getZeroExtendInReg(LHS, VT);
+  RHS = DAG.getZeroExtendInReg(RHS, VT);
+
+  return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
+}
+
 SDOperand DAGTypeLegalizer::PromoteResult_SHL(SDNode *N) {
   return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
                      GetPromotedOp(N->getOperand(0)), N->getOperand(1));