reenable collapse of loadimm+AND -> dep.z (thanks guys)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22944 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index b66a032..bf5aa56 100644
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -1439,7 +1439,7 @@
case MVT::i32:
case MVT::i64: {
Tmp1 = SelectExpr(N.getOperand(0));
-/* FIXME switch (ponderIntegerAndWith(N.getOperand(1), Tmp3)) {
+ switch (ponderIntegerAndWith(N.getOperand(1), Tmp3)) {
case 1: // ANDing a constant that is 2^n-1 for some n
switch (Tmp3) {
case 8: // if AND 0x00000000000000FF, be quaint and use zxt1
@@ -1452,12 +1452,13 @@
BuildMI(BB, IA64::ZXT4, 1, Result).addReg(Tmp1);
break;
default: // otherwise, use dep.z to paste zeros
- BuildMI(BB, IA64::DEPZ, 3, Result).addReg(Tmp1)
+ // FIXME: assert the dep.z is in bounds
+ BuildMI(BB, IA64::DEPZ, 3, Result).addReg(Tmp1)
.addImm(0).addImm(Tmp3);
break;
- }
- return Result; // early exit
- FIXME } */ // fallthrough and emit a simple AND:
+ }
+ return Result; // early exit
+ } // fallthrough and emit a simple AND:
Tmp2 = SelectExpr(N.getOperand(1));
BuildMI(BB, IA64::AND, 2, Result).addReg(Tmp1).addReg(Tmp2);
}