Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
into XXXGenRegisterInfo.inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index 2fcb2d4..de20fb2 100644
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -25,14 +25,18 @@
using namespace llvm;
// runEnums - Print out enum values for all of the registers.
-void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
- CodeGenTarget Target(Records);
- CodeGenRegBank &Bank = Target.getRegBank();
+void
+RegisterInfoEmitter::runEnums(raw_ostream &OS,
+ CodeGenTarget &Target, CodeGenRegBank &Bank) {
const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
EmitSourceFileHeader("Target Register Enum Values", OS);
+
+ OS << "\n#ifdef GET_REGINFO_ENUM\n";
+ OS << "#undef GET_REGINFO_ENUM\n";
+
OS << "namespace llvm {\n\n";
if (!Namespace.empty())
@@ -63,12 +67,33 @@
if (!Namespace.empty())
OS << "}\n";
}
+
+ const std::vector<CodeGenRegisterClass> &RegisterClasses =
+ Target.getRegisterClasses();
+
+ if (!RegisterClasses.empty()) {
+ OS << "\n// Register classes\n";
+ OS << "namespace " << RegisterClasses[0].Namespace << " {\n";
+ OS << "enum {\n";
+ for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
+ if (i) OS << ",\n";
+ OS << " " << RegisterClasses[i].getName() << "RegClassID";
+ OS << " = " << i;
+ }
+ OS << "\n };\n";
+ OS << "}\n";
+ }
+
OS << "} // End llvm namespace \n";
+ OS << "#endif // GET_REGINFO_ENUM\n\n";
}
-void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
+void RegisterInfoEmitter::runHeader(raw_ostream &OS, CodeGenTarget &Target) {
EmitSourceFileHeader("Register Information Header Fragment", OS);
- CodeGenTarget Target(Records);
+
+ OS << "\n#ifdef GET_REGINFO_HEADER\n";
+ OS << "#undef GET_REGINFO_HEADER\n";
+
const std::string &TargetName = Target.getName();
std::string ClassName = TargetName + "GenRegisterInfo";
@@ -100,14 +125,6 @@
OS << "namespace " << RegisterClasses[0].Namespace
<< " { // Register classes\n";
- OS << " enum {\n";
- for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
- if (i) OS << ",\n";
- OS << " " << RegisterClasses[i].getName() << "RegClassID";
- OS << " = " << i;
- }
- OS << "\n };\n\n";
-
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
const CodeGenRegisterClass &RC = RegisterClasses[i];
const std::string &Name = RC.getName();
@@ -129,17 +146,125 @@
OS << "} // end of namespace " << TargetName << "\n\n";
}
OS << "} // End llvm namespace \n";
+ OS << "#endif // GET_REGINFO_HEADER\n\n";
}
//
-// RegisterInfoEmitter::run - Main register file description emitter.
+// runMCDesc - Print out MC register descriptions.
//
-void RegisterInfoEmitter::run(raw_ostream &OS) {
- CodeGenTarget Target(Records);
- CodeGenRegBank &RegBank = Target.getRegBank();
- RegBank.computeDerivedInfo();
+void
+RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
+ CodeGenRegBank &RegBank) {
+ EmitSourceFileHeader("MC Register Information", OS);
- EmitSourceFileHeader("Register Information Source Fragment", OS);
+ OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
+ OS << "#undef GET_REGINFO_MC_DESC\n";
+
+ std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
+ RegBank.computeOverlaps(Overlaps);
+
+ OS << "namespace llvm {\n\n";
+
+ const std::string &TargetName = Target.getName();
+ std::string ClassName = TargetName + "GenMCRegisterInfo";
+ OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
+ << " explicit " << ClassName << "(const MCRegisterDesc *D);\n";
+ OS << "};\n";
+
+ OS << "\nnamespace {\n";
+
+ const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
+
+ // Emit an overlap list for all registers.
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ const CodeGenRegister *Reg = Regs[i];
+ const CodeGenRegister::Set &O = Overlaps[Reg];
+ // Move Reg to the front so TRI::getAliasSet can share the list.
+ OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
+ << getQualifiedName(Reg->TheDef) << ", ";
+ for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
+ I != E; ++I)
+ if (*I != Reg)
+ OS << getQualifiedName((*I)->TheDef) << ", ";
+ OS << "0 };\n";
+ }
+
+ // Emit the empty sub-registers list
+ OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
+ // Loop over all of the registers which have sub-registers, emitting the
+ // sub-registers list to memory.
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ const CodeGenRegister &Reg = *Regs[i];
+ if (Reg.getSubRegs().empty())
+ continue;
+ // getSubRegs() orders by SubRegIndex. We want a topological order.
+ SetVector<CodeGenRegister*> SR;
+ Reg.addSubRegsPreOrder(SR);
+ OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
+ for (unsigned j = 0, je = SR.size(); j != je; ++j)
+ OS << getQualifiedName(SR[j]->TheDef) << ", ";
+ OS << "0 };\n";
+ }
+
+ // Emit the empty super-registers list
+ OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
+ // Loop over all of the registers which have super-registers, emitting the
+ // super-registers list to memory.
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ const CodeGenRegister &Reg = *Regs[i];
+ const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
+ if (SR.empty())
+ continue;
+ OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
+ for (unsigned j = 0, je = SR.size(); j != je; ++j)
+ OS << getQualifiedName(SR[j]->TheDef) << ", ";
+ OS << "0 };\n";
+ }
+
+ OS << "\n const MCRegisterDesc " << TargetName
+ << "RegDesc[] = { // Descriptors\n";
+ OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
+
+ // Now that register alias and sub-registers sets have been emitted, emit the
+ // register descriptors now.
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ const CodeGenRegister &Reg = *Regs[i];
+ OS << " { \"";
+ OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
+ if (!Reg.getSubRegs().empty())
+ OS << Reg.getName() << "_SubRegsSet,\t";
+ else
+ OS << "Empty_SubRegsSet,\t";
+ if (!Reg.getSuperRegs().empty())
+ OS << Reg.getName() << "_SuperRegsSet";
+ else
+ OS << "Empty_SuperRegsSet";
+ OS << " },\n";
+ }
+ OS << " };\n"; // End of register descriptors...
+
+ OS << "}\n\n"; // End of anonymous namespace...
+
+ // MCRegisterInfo initialization routine.
+ OS << "static inline void Init" << TargetName
+ << "MCRegisterInfo(MCRegisterInfo *RI) {\n";
+ OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
+ << Regs.size()+1 << ");\n}\n\n";
+
+ OS << "} // End llvm namespace \n";
+ OS << "#endif // GET_REGINFO_MC_DESC\n\n";
+}
+
+//
+// runTargetDesc - Output the target register and register file descriptions.
+//
+void
+RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
+ CodeGenRegBank &RegBank){
+ EmitSourceFileHeader("Target Register and Register Classes Information", OS);
+
+ OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
+ OS << "#undef GET_REGINFO_TARGET_DESC\n";
OS << "namespace llvm {\n\n";
@@ -614,102 +739,16 @@
OS << " };\n}\n\n";
OS << "} // End llvm namespace \n";
+ OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
}
-void RegisterInfoEmitter::runDesc(raw_ostream &OS) {
+void RegisterInfoEmitter::run(raw_ostream &OS) {
CodeGenTarget Target(Records);
CodeGenRegBank &RegBank = Target.getRegBank();
RegBank.computeDerivedInfo();
- std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
- RegBank.computeOverlaps(Overlaps);
- OS << "namespace llvm {\n\n";
-
- const std::string &TargetName = Target.getName();
- std::string ClassName = TargetName + "GenMCRegisterInfo";
- OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
- << " explicit " << ClassName << "(const MCRegisterDesc *D);\n";
- OS << "};\n";
-
- OS << "\nnamespace {\n";
-
- const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
-
- // Emit an overlap list for all registers.
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- const CodeGenRegister *Reg = Regs[i];
- const CodeGenRegister::Set &O = Overlaps[Reg];
- // Move Reg to the front so TRI::getAliasSet can share the list.
- OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
- << getQualifiedName(Reg->TheDef) << ", ";
- for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
- I != E; ++I)
- if (*I != Reg)
- OS << getQualifiedName((*I)->TheDef) << ", ";
- OS << "0 };\n";
- }
-
- // Emit the empty sub-registers list
- OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
- // Loop over all of the registers which have sub-registers, emitting the
- // sub-registers list to memory.
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- const CodeGenRegister &Reg = *Regs[i];
- if (Reg.getSubRegs().empty())
- continue;
- // getSubRegs() orders by SubRegIndex. We want a topological order.
- SetVector<CodeGenRegister*> SR;
- Reg.addSubRegsPreOrder(SR);
- OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
- for (unsigned j = 0, je = SR.size(); j != je; ++j)
- OS << getQualifiedName(SR[j]->TheDef) << ", ";
- OS << "0 };\n";
- }
-
- // Emit the empty super-registers list
- OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
- // Loop over all of the registers which have super-registers, emitting the
- // super-registers list to memory.
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- const CodeGenRegister &Reg = *Regs[i];
- const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
- if (SR.empty())
- continue;
- OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
- for (unsigned j = 0, je = SR.size(); j != je; ++j)
- OS << getQualifiedName(SR[j]->TheDef) << ", ";
- OS << "0 };\n";
- }
-
- OS << "\n const MCRegisterDesc " << TargetName
- << "RegDesc[] = { // Descriptors\n";
- OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
-
- // Now that register alias and sub-registers sets have been emitted, emit the
- // register descriptors now.
- for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- const CodeGenRegister &Reg = *Regs[i];
- OS << " { \"";
- OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
- if (!Reg.getSubRegs().empty())
- OS << Reg.getName() << "_SubRegsSet,\t";
- else
- OS << "Empty_SubRegsSet,\t";
- if (!Reg.getSuperRegs().empty())
- OS << Reg.getName() << "_SuperRegsSet";
- else
- OS << "Empty_SuperRegsSet";
- OS << " },\n";
- }
- OS << " };\n"; // End of register descriptors...
-
- OS << "}\n\n"; // End of anonymous namespace...
-
- // MCRegisterInfo initialization routine.
- OS << "static inline void Init" << TargetName
- << "MCRegisterInfo(MCRegisterInfo *RI) {\n";
- OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
- << Regs.size()+1 << ");\n}\n\n";
-
- OS << "} // End llvm namespace \n";
+ runEnums(OS, Target, RegBank);
+ runHeader(OS, Target);
+ runMCDesc(OS, Target, RegBank);
+ runTargetDesc(OS, Target, RegBank);
}
diff --git a/utils/TableGen/RegisterInfoEmitter.h b/utils/TableGen/RegisterInfoEmitter.h
index 6bf14b2..d625b7d 100644
--- a/utils/TableGen/RegisterInfoEmitter.h
+++ b/utils/TableGen/RegisterInfoEmitter.h
@@ -20,22 +20,28 @@
namespace llvm {
+class CodeGenRegBank;
+class CodeGenTarget;
+
class RegisterInfoEmitter : public TableGenBackend {
RecordKeeper &Records;
public:
RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
- // run - Output the register file description, returning true on failure.
- void run(raw_ostream &o);
+ // runEnums - Print out enum values for all of the registers.
+ void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
// runHeader - Emit a header fragment for the register info emitter.
- void runHeader(raw_ostream &o);
+ void runHeader(raw_ostream &o, CodeGenTarget &Target);
- // runEnums - Print out enum values for all of the registers.
- void runEnums(raw_ostream &o);
+ // runMCDesc - Print out MC register descriptions.
+ void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
- // runDesc - Print out register descriptions.
- void runDesc(raw_ostream &o);
+ // runTargetDesc - Output the target register and register file descriptions.
+ void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
+
+ // run - Output the register file description.
+ void run(raw_ostream &o);
};
} // End llvm namespace
diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp
index b11ef6f..6f220c9 100644
--- a/utils/TableGen/TableGen.cpp
+++ b/utils/TableGen/TableGen.cpp
@@ -54,7 +54,7 @@
enum ActionType {
PrintRecords,
GenEmitter,
- GenRegisterEnums, GenRegisterDesc, GenRegisterInfo, GenRegisterInfoHeader,
+ GenRegisterInfo,
GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher,
GenARMDecoder,
GenDisassembler,
@@ -93,14 +93,8 @@
"Print all records to stdout (default)"),
clEnumValN(GenEmitter, "gen-emitter",
"Generate machine code emitter"),
- clEnumValN(GenRegisterEnums, "gen-register-enums",
- "Generate enum values for registers"),
- clEnumValN(GenRegisterDesc, "gen-register-desc",
- "Generate register descriptions"),
clEnumValN(GenRegisterInfo, "gen-register-info",
- "Generate registers & reg-classes info"),
- clEnumValN(GenRegisterInfoHeader, "gen-register-info-header",
- "Generate registers & reg-classes info header"),
+ "Generate registers and register classes info"),
clEnumValN(GenInstrEnums, "gen-instr-enums",
"Generate enum values for instructions"),
clEnumValN(GenInstrs, "gen-instr-desc",
@@ -263,18 +257,9 @@
case GenEmitter:
CodeEmitterGen(Records).run(Out.os());
break;
- case GenRegisterEnums:
- RegisterInfoEmitter(Records).runEnums(Out.os());
- break;
- case GenRegisterDesc:
- RegisterInfoEmitter(Records).runDesc(Out.os());
- break;
case GenRegisterInfo:
RegisterInfoEmitter(Records).run(Out.os());
break;
- case GenRegisterInfoHeader:
- RegisterInfoEmitter(Records).runHeader(Out.os());
- break;
case GenInstrEnums:
InstrEnumEmitter(Records).run(Out.os());
break;