commit 743e19983effd486c1911f5b797aea7133ea154c
author Chad Rosier <mcrosier@apple.com> Wed Feb 08 02:45:44 2012 +0000
committer Chad Rosier <mcrosier@apple.com> Wed Feb 08 02:45:44 2012 +0000
tree a3ecd0cd8b25cf508bdfa54a50dfeb4ef89f1176
parent 176346d021aade8949c5d33e280d835b30a6b5c9

[fast-isel] Add support for SUBs with non-legal types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150047 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMFastISel.cpp

diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index faa3e59..39b3bd4 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -1749,6 +1749,9 @@
     case ISD::OR:
       Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
       break;
+    case ISD::SUB:
+      Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
+      break;
   }
 
   unsigned SrcReg1 = getRegForValue(I->getOperand(0));
@@ -2509,6 +2512,8 @@
       return SelectBinaryIntOp(I, ISD::ADD);
     case Instruction::Or:
       return SelectBinaryIntOp(I, ISD::OR);
+    case Instruction::Sub:
+      return SelectBinaryIntOp(I, ISD::SUB);
     case Instruction::FAdd:
       return SelectBinaryFPOp(I, ISD::FADD);
     case Instruction::FSub: