rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 62d4da4..2105f14 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -55,7 +55,7 @@
void emitInstruction(const MachineInstr &MI);
int getMachineOpValue(const MachineInstr &MI, unsigned OpIndex);
- unsigned getBaseOpcodeFor(const TargetInstrDescriptor *TID);
+ unsigned getBaseOpcodeFor(const TargetInstrDesc &TID);
unsigned getBinaryCodeForInstr(const MachineInstr &MI);
void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
@@ -103,8 +103,8 @@
}
/// getBaseOpcodeFor - Return the opcode value
-unsigned Emitter::getBaseOpcodeFor(const TargetInstrDescriptor *TID) {
- return (TID->TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
+unsigned Emitter::getBaseOpcodeFor(const TargetInstrDesc &TID) {
+ return (TID.TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
}
/// getShiftOp - Verify which is the shift opcode (bit[6:5]) of the
@@ -201,15 +201,15 @@
}
unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
- const TargetInstrDescriptor *Desc = MI.getDesc();
- unsigned opcode = Desc->Opcode;
+ const TargetInstrDesc &Desc = MI.getDesc();
+ unsigned opcode = Desc.Opcode;
// initial instruction mask
unsigned Value = 0xE0000000;
unsigned op;
- switch (Desc->TSFlags & ARMII::AddrModeMask) {
+ switch (Desc.TSFlags & ARMII::AddrModeMask) {
case ARMII::AddrModeNone: {
- switch(Desc->TSFlags & ARMII::FormMask) {
+ switch(Desc.TSFlags & ARMII::FormMask) {
default: {
assert(0 && "Unknown instruction subtype!");
// treat special instruction CLZ
@@ -241,7 +241,7 @@
unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
Value |= BaseOpcode << 4;
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+ unsigned Format = (Desc.TSFlags & ARMII::FormMask);
if (Format == ARMII::MulSMUL)
Value |= 1 << 22;
@@ -342,7 +342,7 @@
// treat 3 special instructions: MOVsra_flag, MOVsrl_flag and
// MOVrx.
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+ unsigned Format = Desc.TSFlags & ARMII::FormMask;
if (Format == ARMII::DPRdMisc) {
Value |= getMachineOpValue(MI,0) << ARMII::RegRdShift;
Value |= getMachineOpValue(MI,1);
@@ -499,7 +499,7 @@
// bit 26 is always 1
Value |= 1 << 26;
- unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
+ unsigned Index = Desc.TSFlags & ARMII::IndexModeMask;
// if the instruction uses offset addressing or pre-indexed addressing,
// set bit P(24) to 1
if (Index == ARMII::IndexModePre || Index == 0)
@@ -508,7 +508,7 @@
if (Index == ARMII::IndexModePre)
Value |= 1 << 21;
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+ unsigned Format = Desc.TSFlags & ARMII::FormMask;
// If it is a load instruction (except LDRD), set bit L(20) to 1
if (Format == ARMII::LdFrm)
Value |= 1 << ARMII::L_BitShift;
@@ -555,14 +555,13 @@
break;
}
case ARMII::AddrMode3: {
-
- unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
+ unsigned Index = Desc.TSFlags & ARMII::IndexModeMask;
// if the instruction uses offset addressing or pre-indexed addressing,
// set bit P(24) to 1
if (Index == ARMII::IndexModePre || Index == 0)
Value |= 1 << ARMII::IndexShift;
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+ unsigned Format = Desc.TSFlags & ARMII::FormMask;
// If it is a load instruction (except LDRD), set bit L(20) to 1
if (Format == ARMII::LdFrm && opcode != ARM::LDRD)
Value |= 1 << ARMII::L_BitShift;
@@ -607,7 +606,7 @@
// bit 27 is always 1
Value |= 1 << 27;
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+ unsigned Format = Desc.TSFlags & ARMII::FormMask;
// if it is a load instr, set bit L(20) to 1
if (Format == ARMII::LdFrm)
Value |= 1 << ARMII::L_BitShift;
diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp
index 5f54e1f..ea1ee9e 100644
--- a/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -371,7 +371,7 @@
MBBSize += ARM::GetInstSize(I);
int Opc = I->getOpcode();
- if (I->getDesc()->isBranch()) {
+ if (I->getDesc().isBranch()) {
bool isCond = false;
unsigned Bits = 0;
unsigned Scale = 1;
@@ -423,7 +423,7 @@
// Basic size info comes from the TSFlags field.
unsigned Bits = 0;
unsigned Scale = 1;
- unsigned TSFlags = I->getDesc()->TSFlags;
+ unsigned TSFlags = I->getDesc().TSFlags;
switch (TSFlags & ARMII::AddrModeMask) {
default:
// Constant pool entries can reach anything.
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 2e9d802..513f9ec 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -63,7 +63,7 @@
return true;
case ARM::MOVr:
case ARM::tMOVr:
- assert(MI.getDesc()->getNumOperands() >= 2 &&
+ assert(MI.getDesc().getNumOperands() >= 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"Invalid ARM MOV instruction");
@@ -180,7 +180,7 @@
return NULL;
MachineInstr *MI = MBBI;
- unsigned TSFlags = MI->getDesc()->TSFlags;
+ unsigned TSFlags = MI->getDesc().TSFlags;
bool isPre = false;
switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
default: return NULL;
@@ -200,9 +200,9 @@
MachineInstr *UpdateMI = NULL;
MachineInstr *MemMI = NULL;
unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
- const TargetInstrDescriptor *TID = MI->getDesc();
- unsigned NumOps = TID->getNumOperands();
- bool isLoad = TID->isSimpleLoad();
+ const TargetInstrDesc &TID = MI->getDesc();
+ unsigned NumOps = TID.getNumOperands();
+ bool isLoad = TID.isSimpleLoad();
const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
const MachineOperand &Base = MI->getOperand(2);
const MachineOperand &Offset = MI->getOperand(NumOps-3);
@@ -837,8 +837,8 @@
bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const {
- const TargetInstrDescriptor *TID = MI->getDesc();
- if (!TID->getImplicitDefs() && !TID->hasOptionalDef())
+ const TargetInstrDesc &TID = MI->getDesc();
+ if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
return false;
bool Found = false;
@@ -870,8 +870,8 @@
const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
// Basic size info comes from the TSFlags field.
- const TargetInstrDescriptor *TID = MI->getDesc();
- unsigned TSFlags = TID->TSFlags;
+ const TargetInstrDesc &TID = MI->getDesc();
+ unsigned TSFlags = TID.TSFlags;
switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
default:
@@ -897,9 +897,9 @@
case ARM::tBR_JTr: {
// These are jumptable branches, i.e. a branch followed by an inlined
// jumptable. The size is 4 + 4 * number of entries.
- unsigned NumOps = TID->getNumOperands();
+ unsigned NumOps = TID.getNumOperands();
MachineOperand JTOP =
- MI->getOperand(NumOps - (TID->isPredicable() ? 3 : 2));
+ MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
unsigned JTI = JTOP.getIndex();
MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 29da83d..347ed8b 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -599,8 +599,8 @@
unsigned Base = MBBI->getOperand(1).getReg();
unsigned PredReg = 0;
ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
- const TargetInstrDescriptor *TID = MBBI->getDesc();
- unsigned OffField = MBBI->getOperand(TID->getNumOperands()-3).getImm();
+ unsigned NumOperands = MBBI->getDesc().getNumOperands();
+ unsigned OffField = MBBI->getOperand(NumOperands-3).getImm();
int Offset = isAM2
? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;
if (isAM2) {
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index fc72132..01d0841 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -581,7 +581,7 @@
}
unsigned Opcode = MI.getOpcode();
- const TargetInstrDescriptor &Desc = *MI.getDesc();
+ const TargetInstrDesc &Desc = MI.getDesc();
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
bool isSub = false;
@@ -1036,7 +1036,7 @@
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
if (I->getOperand(i).isFrameIndex()) {
unsigned Opcode = I->getOpcode();
- const TargetInstrDescriptor &Desc = TII.get(Opcode);
+ const TargetInstrDesc &Desc = TII.get(Opcode);
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
if (AddrMode == ARMII::AddrMode3) {
Limit = (1 << 8) - 1;
diff --git a/lib/Target/Mips/MipsDelaySlotFiller.cpp b/lib/Target/Mips/MipsDelaySlotFiller.cpp
index c3f92f8..881cd12 100644
--- a/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -59,7 +59,7 @@
{
bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
- if (I->getDesc()->hasDelaySlot()) {
+ if (I->getDesc().hasDelaySlot()) {
MachineBasicBlock::iterator J = I;
++J;
BuildMI(MBB, J, TII->get(Mips::NOP));
diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp
index 8896b35..85c1048 100644
--- a/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/lib/Target/Mips/MipsInstrInfo.cpp
@@ -175,7 +175,7 @@
// If there is only one terminator instruction, process it.
unsigned LastOpc = LastInst->getOpcode();
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
- if (!LastInst->getDesc()->isBranch())
+ if (!LastInst->getDesc().isBranch())
return true;
// Unconditional branch
@@ -259,7 +259,7 @@
} else {
// Conditional branch.
unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
- const TargetInstrDescriptor &TID = get(Opc);
+ const TargetInstrDesc &TID = get(Opc);
if (TID.getNumOperands() == 3)
BuildMI(&MBB, TID).addReg(Cond[1].getReg())
@@ -275,15 +275,13 @@
// Two-way Conditional branch.
unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
- const TargetInstrDescriptor &TID = get(Opc);
+ const TargetInstrDesc &TID = get(Opc);
if (TID.getNumOperands() == 3)
- BuildMI(&MBB, TID).addReg(Cond[1].getReg())
- .addReg(Cond[2].getReg())
+ BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
.addMBB(TBB);
else
- BuildMI(&MBB, TID).addReg(Cond[1].getReg())
- .addMBB(TBB);
+ BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addMBB(TBB);
BuildMI(&MBB, get(Mips::J)).addMBB(FBB);
return 2;
diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
index 3c7fcfa..58df0d6 100644
--- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp
+++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
@@ -70,7 +70,7 @@
}
Opcode -= ISD::BUILTIN_OP_END;
- const TargetInstrDescriptor &TID = TII.get(Opcode);
+ const TargetInstrDesc &TID = TII.get(Opcode);
isLoad = TID.isSimpleLoad();
isStore = TID.mayStore();
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 7ab17bc..6e8cebd 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -262,13 +262,13 @@
// Find all return blocks, outputting a restore in each epilog.
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
- if (!BB->empty() && BB->back().getDesc()->isReturn()) {
+ if (!BB->empty() && BB->back().getDesc().isReturn()) {
IP = BB->end(); --IP;
// Skip over all terminator instructions, which are part of the return
// sequence.
MachineBasicBlock::iterator I2 = IP;
- while (I2 != BB->begin() && (--I2)->getDesc()->isTerminator())
+ while (I2 != BB->begin() && (--I2)->getDesc().isTerminator())
IP = I2;
// Emit: MTVRSAVE InVRSave
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 866c2bf..19d7afa 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -540,7 +540,7 @@
// epilog blocks.
for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
// If last instruction is a return instruction, add an epilogue
- if (!I->empty() && I->back().getDesc()->isReturn()) {
+ if (!I->empty() && I->back().getDesc().isReturn()) {
bool FoundIt = false;
for (MBBI = I->end(); MBBI != I->begin(); ) {
--MBBI;
diff --git a/lib/Target/Sparc/DelaySlotFiller.cpp b/lib/Target/Sparc/DelaySlotFiller.cpp
index 00d14f2..8185732 100644
--- a/lib/Target/Sparc/DelaySlotFiller.cpp
+++ b/lib/Target/Sparc/DelaySlotFiller.cpp
@@ -65,7 +65,7 @@
bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
- if (I->getDesc()->hasDelaySlot()) {
+ if (I->getDesc().hasDelaySlot()) {
MachineBasicBlock::iterator J = I;
++J;
BuildMI(MBB, J, TII->get(SP::NOP));
diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp
index 5342dd1..10a5cdb 100644
--- a/lib/Target/TargetInstrInfo.cpp
+++ b/lib/Target/TargetInstrInfo.cpp
@@ -18,7 +18,7 @@
/// findTiedToSrcOperand - Returns the operand that is tied to the specified
/// dest operand. Returns -1 if there isn't one.
-int TargetInstrDescriptor::findTiedToSrcOperand(unsigned OpNum) const {
+int TargetInstrDesc::findTiedToSrcOperand(unsigned OpNum) const {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
if (i == OpNum)
continue;
@@ -29,22 +29,22 @@
}
-TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc,
+TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc,
unsigned numOpcodes)
- : desc(Desc), NumOpcodes(numOpcodes) {
+ : Descriptors(Desc), NumOpcodes(numOpcodes) {
}
TargetInstrInfo::~TargetInstrInfo() {
}
bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
- const TargetInstrDescriptor *TID = MI->getDesc();
- if (!TID->isTerminator()) return false;
+ const TargetInstrDesc &TID = MI->getDesc();
+ if (!TID.isTerminator()) return false;
// Conditional branch is a special case.
- if (TID->isBranch() && !TID->isBarrier())
+ if (TID.isBranch() && !TID.isBarrier())
return true;
- if (!TID->isPredicable())
+ if (!TID.isPredicable())
return true;
return !isPredicated(MI);
}
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index d25ede1..bd9e5c6 100644
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -60,7 +60,7 @@
}
void emitInstruction(const MachineInstr &MI,
- const TargetInstrDescriptor *Desc);
+ const TargetInstrDesc *Desc);
private:
void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
@@ -115,10 +115,10 @@
MCE.StartMachineBasicBlock(MBB);
for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
I != E; ++I) {
- const TargetInstrDescriptor *Desc = I->getDesc();
- emitInstruction(*I, Desc);
+ const TargetInstrDesc &Desc = I->getDesc();
+ emitInstruction(*I, &Desc);
// MOVPC32r is basically a call plus a pop instruction.
- if (Desc->Opcode == X86::MOVPC32r)
+ if (Desc.getOpcode() == X86::MOVPC32r)
emitInstruction(*I, &II->get(X86::POP32r));
NumEmitted++; // Keep track of the # of mi's emitted
}
@@ -394,7 +394,7 @@
}
}
-static unsigned sizeOfImm(const TargetInstrDescriptor *Desc) {
+static unsigned sizeOfImm(const TargetInstrDesc *Desc) {
switch (Desc->TSFlags & X86II::ImmMask) {
case X86II::Imm8: return 1;
case X86II::Imm16: return 2;
@@ -436,18 +436,18 @@
/// size, and 3) use of X86-64 extended registers.
unsigned Emitter::determineREX(const MachineInstr &MI) {
unsigned REX = 0;
- const TargetInstrDescriptor *Desc = MI.getDesc();
+ const TargetInstrDesc &Desc = MI.getDesc();
// Pseudo instructions do not need REX prefix byte.
- if ((Desc->TSFlags & X86II::FormMask) == X86II::Pseudo)
+ if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
return 0;
- if (Desc->TSFlags & X86II::REX_W)
+ if (Desc.TSFlags & X86II::REX_W)
REX |= 1 << 3;
- unsigned NumOps = Desc->getNumOperands();
+ unsigned NumOps = Desc.getNumOperands();
if (NumOps) {
bool isTwoAddr = NumOps > 1 &&
- Desc->getOperandConstraint(1, TOI::TIED_TO) != -1;
+ Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
// If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
unsigned i = isTwoAddr ? 1 : 0;
@@ -460,7 +460,7 @@
}
}
- switch (Desc->TSFlags & X86II::FormMask) {
+ switch (Desc.TSFlags & X86II::FormMask) {
case X86II::MRMInitReg:
if (isX86_64ExtendedReg(MI.getOperand(0)))
REX |= (1 << 0) | (1 << 2);
@@ -528,7 +528,7 @@
}
void Emitter::emitInstruction(const MachineInstr &MI,
- const TargetInstrDescriptor *Desc) {
+ const TargetInstrDesc *Desc) {
unsigned Opcode = Desc->Opcode;
// Emit the repeat opcode prefix as needed.
diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp
index 3d0d423..1b3e0b8 100644
--- a/lib/Target/X86/X86FloatingPoint.cpp
+++ b/lib/Target/X86/X86FloatingPoint.cpp
@@ -205,7 +205,7 @@
for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
MachineInstr *MI = I;
- unsigned Flags = MI->getDesc()->TSFlags;
+ unsigned Flags = MI->getDesc().TSFlags;
if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
continue; // Efficiently ignore non-fp insts!
@@ -597,7 +597,7 @@
///
void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
- unsigned NumOps = MI->getDesc()->getNumOperands();
+ unsigned NumOps = MI->getDesc().getNumOperands();
assert((NumOps == 5 || NumOps == 1) &&
"Can only handle fst* & ftst instructions!");
@@ -657,7 +657,7 @@
///
void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
- unsigned NumOps = MI->getDesc()->getNumOperands();
+ unsigned NumOps = MI->getDesc().getNumOperands();
assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
// Is this the last use of the source register?
@@ -766,7 +766,7 @@
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
- unsigned NumOperands = MI->getDesc()->getNumOperands();
+ unsigned NumOperands = MI->getDesc().getNumOperands();
assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
unsigned Dest = getFPReg(MI->getOperand(0));
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
@@ -864,7 +864,7 @@
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
- unsigned NumOperands = MI->getDesc()->getNumOperands();
+ unsigned NumOperands = MI->getDesc().getNumOperands();
assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index cae382d..42e4127 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -1243,13 +1243,13 @@
}
bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
- const TargetInstrDescriptor *TID = MI->getDesc();
- if (!TID->isTerminator()) return false;
+ const TargetInstrDesc &TID = MI->getDesc();
+ if (!TID.isTerminator()) return false;
// Conditional branch is a special case.
- if (TID->isBranch() && !TID->isBarrier())
+ if (TID.isBranch() && !TID.isBarrier())
return true;
- if (!TID->isPredicable())
+ if (!TID.isPredicable())
return true;
return !isPredicated(MI);
}
@@ -1276,7 +1276,7 @@
// If there is only one terminator instruction, process it.
if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
- if (!LastInst->getDesc()->isBranch())
+ if (!LastInst->getDesc().isBranch())
return true;
// If the block ends with a branch there are 3 possibilities:
@@ -1640,7 +1640,7 @@
MIB.addImm(1).addReg(0).addImm(0);
// Loop over the rest of the ri operands, converting them over.
- unsigned NumOps = MI->getDesc()->getNumOperands()-2;
+ unsigned NumOps = MI->getDesc().getNumOperands()-2;
for (unsigned i = 0; i != NumOps; ++i) {
MachineOperand &MO = MI->getOperand(i+2);
MIB = X86InstrAddOperand(MIB, MO);
@@ -1692,9 +1692,9 @@
SmallVector<MachineOperand,4> &MOs) const {
const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
bool isTwoAddrFold = false;
- unsigned NumOps = MI->getDesc()->getNumOperands();
+ unsigned NumOps = MI->getDesc().getNumOperands();
bool isTwoAddr = NumOps > 1 &&
- MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1;
+ MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
MachineInstr *NewMI = NULL;
// Folding a memory location into the two-address part of a two-address
@@ -1798,7 +1798,7 @@
return NULL;
SmallVector<MachineOperand,4> MOs;
- unsigned NumOps = LoadMI->getDesc()->getNumOperands();
+ unsigned NumOps = LoadMI->getDesc().getNumOperands();
for (unsigned i = NumOps - 4; i != NumOps; ++i)
MOs.push_back(LoadMI->getOperand(i));
return foldMemoryOperand(MI, Ops[0], MOs);
@@ -1826,9 +1826,9 @@
unsigned OpNum = Ops[0];
unsigned Opc = MI->getOpcode();
- unsigned NumOps = MI->getDesc()->getNumOperands();
+ unsigned NumOps = MI->getDesc().getNumOperands();
bool isTwoAddr = NumOps > 1 &&
- MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1;
+ MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
// Folding a memory location into the two-address part of a two-address
// instruction is different than folding it other places. It requires
@@ -1880,7 +1880,7 @@
return false;
UnfoldStore &= FoldedStore;
- const TargetInstrDescriptor &TID = get(Opc);
+ const TargetInstrDesc &TID = get(Opc);
const TargetOperandInfo &TOI = TID.OpInfo[Index];
const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
@@ -1979,7 +1979,7 @@
unsigned Index = I->second.second & 0xf;
bool FoldedLoad = I->second.second & (1 << 4);
bool FoldedStore = I->second.second & (1 << 5);
- const TargetInstrDescriptor &TID = get(Opc);
+ const TargetInstrDesc &TID = get(Opc);
const TargetOperandInfo &TOI = TID.OpInfo[Index];
const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index c0aefb4..27675b9 100644
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -364,7 +364,7 @@
// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
// specified machine instruction.
//
- unsigned char getBaseOpcodeFor(const TargetInstrDescriptor *TID) const {
+ unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const {
return TID->TSFlags >> X86II::OpcodeShift;
}
unsigned char getBaseOpcodeFor(unsigned Opcode) const {
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 1e54417..56523eb 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -729,7 +729,7 @@
MachineBasicBlock::iterator PI = prior(MBBI);
unsigned Opc = PI->getOpcode();
if (Opc != X86::POP32r && Opc != X86::POP64r &&
- !PI->getDesc()->isTerminator())
+ !PI->getDesc().isTerminator())
break;
--MBBI;
}