commit 749c6f6b5ed301c84aac562e414486549d7b98eb
author Chris Lattner <sabre@nondot.org> Mon Jan 07 07:27:27 2008 +0000
committer Chris Lattner <sabre@nondot.org> Mon Jan 07 07:27:27 2008 +0000
tree 275f34b73cd0673d5e8fdcfe02cdb6d60c5422c2
parent 682b8aed0779ac0c9a6a13d79ccc1cff3e9730cf

rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMInstrInfo.cpp

diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 2e9d802..513f9ec 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -63,7 +63,7 @@
     return true;
   case ARM::MOVr:
   case ARM::tMOVr:
-    assert(MI.getDesc()->getNumOperands() >= 2 &&
+    assert(MI.getDesc().getNumOperands() >= 2 &&
            MI.getOperand(0).isRegister() &&
            MI.getOperand(1).isRegister() &&
            "Invalid ARM MOV instruction");
@@ -180,7 +180,7 @@
     return NULL;
 
   MachineInstr *MI = MBBI;
-  unsigned TSFlags = MI->getDesc()->TSFlags;
+  unsigned TSFlags = MI->getDesc().TSFlags;
   bool isPre = false;
   switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
   default: return NULL;
@@ -200,9 +200,9 @@
   MachineInstr *UpdateMI = NULL;
   MachineInstr *MemMI = NULL;
   unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
-  const TargetInstrDescriptor *TID = MI->getDesc();
-  unsigned NumOps = TID->getNumOperands();
-  bool isLoad = TID->isSimpleLoad();
+  const TargetInstrDesc &TID = MI->getDesc();
+  unsigned NumOps = TID.getNumOperands();
+  bool isLoad = TID.isSimpleLoad();
   const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
   const MachineOperand &Base = MI->getOperand(2);
   const MachineOperand &Offset = MI->getOperand(NumOps-3);
@@ -837,8 +837,8 @@
 
 bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
                                     std::vector<MachineOperand> &Pred) const {
-  const TargetInstrDescriptor *TID = MI->getDesc();
-  if (!TID->getImplicitDefs() && !TID->hasOptionalDef())
+  const TargetInstrDesc &TID = MI->getDesc();
+  if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
     return false;
 
   bool Found = false;
@@ -870,8 +870,8 @@
   const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
 
   // Basic size info comes from the TSFlags field.
-  const TargetInstrDescriptor *TID = MI->getDesc();
-  unsigned TSFlags = TID->TSFlags;
+  const TargetInstrDesc &TID = MI->getDesc();
+  unsigned TSFlags = TID.TSFlags;
   
   switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
   default:
@@ -897,9 +897,9 @@
     case ARM::tBR_JTr: {
       // These are jumptable branches, i.e. a branch followed by an inlined
       // jumptable. The size is 4 + 4 * number of entries.
-      unsigned NumOps = TID->getNumOperands();
+      unsigned NumOps = TID.getNumOperands();
       MachineOperand JTOP =
-        MI->getOperand(NumOps - (TID->isPredicable() ? 3 : 2));
+        MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
       unsigned JTI = JTOP.getIndex();
       MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
       const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();