commit 749c6f6b5ed301c84aac562e414486549d7b98eb
author Chris Lattner <sabre@nondot.org> Mon Jan 07 07:27:27 2008 +0000
committer Chris Lattner <sabre@nondot.org> Mon Jan 07 07:27:27 2008 +0000
tree 275f34b73cd0673d5e8fdcfe02cdb6d60c5422c2
parent 682b8aed0779ac0c9a6a13d79ccc1cff3e9730cf

rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86CodeEmitter.cpp

diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index d25ede1..bd9e5c6 100644
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -60,7 +60,7 @@
     }
 
     void emitInstruction(const MachineInstr &MI,
-                         const TargetInstrDescriptor *Desc);
+                         const TargetInstrDesc *Desc);
 
   private:
     void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
@@ -115,10 +115,10 @@
       MCE.StartMachineBasicBlock(MBB);
       for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
            I != E; ++I) {
-        const TargetInstrDescriptor *Desc = I->getDesc();
-        emitInstruction(*I, Desc);
+        const TargetInstrDesc &Desc = I->getDesc();
+        emitInstruction(*I, &Desc);
         // MOVPC32r is basically a call plus a pop instruction.
-        if (Desc->Opcode == X86::MOVPC32r)
+        if (Desc.getOpcode() == X86::MOVPC32r)
           emitInstruction(*I, &II->get(X86::POP32r));
         NumEmitted++;  // Keep track of the # of mi's emitted
       }
@@ -394,7 +394,7 @@
   }
 }
 
-static unsigned sizeOfImm(const TargetInstrDescriptor *Desc) {
+static unsigned sizeOfImm(const TargetInstrDesc *Desc) {
   switch (Desc->TSFlags & X86II::ImmMask) {
   case X86II::Imm8:   return 1;
   case X86II::Imm16:  return 2;
@@ -436,18 +436,18 @@
 /// size, and 3) use of X86-64 extended registers.
 unsigned Emitter::determineREX(const MachineInstr &MI) {
   unsigned REX = 0;
-  const TargetInstrDescriptor *Desc = MI.getDesc();
+  const TargetInstrDesc &Desc = MI.getDesc();
 
   // Pseudo instructions do not need REX prefix byte.
-  if ((Desc->TSFlags & X86II::FormMask) == X86II::Pseudo)
+  if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
     return 0;
-  if (Desc->TSFlags & X86II::REX_W)
+  if (Desc.TSFlags & X86II::REX_W)
     REX |= 1 << 3;
 
-  unsigned NumOps = Desc->getNumOperands();
+  unsigned NumOps = Desc.getNumOperands();
   if (NumOps) {
     bool isTwoAddr = NumOps > 1 &&
-      Desc->getOperandConstraint(1, TOI::TIED_TO) != -1;
+      Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
 
     // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
     unsigned i = isTwoAddr ? 1 : 0;
@@ -460,7 +460,7 @@
       }
     }
 
-    switch (Desc->TSFlags & X86II::FormMask) {
+    switch (Desc.TSFlags & X86II::FormMask) {
     case X86II::MRMInitReg:
       if (isX86_64ExtendedReg(MI.getOperand(0)))
         REX |= (1 << 0) | (1 << 2);
@@ -528,7 +528,7 @@
 }
 
 void Emitter::emitInstruction(const MachineInstr &MI,
-                              const TargetInstrDescriptor *Desc) {
+                              const TargetInstrDesc *Desc) {
   unsigned Opcode = Desc->Opcode;
 
   // Emit the repeat opcode prefix as needed.