Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
would have been a Godsend here!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47625 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index dacc50d..31055b2 100644
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -273,7 +273,7 @@
switch (MO.getType()) {
case MachineOperand::MO_Register:
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
- O << TM.getRegisterInfo()->get(MO.getReg()).Name;
+ O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
else
assert(0 && "not implemented");
break;
@@ -393,7 +393,7 @@
const MachineOperand &MO3 = MI->getOperand(Op+2);
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
- O << TM.getRegisterInfo()->get(MO1.getReg()).Name;
+ O << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
// Print the shift opc.
O << ", "
@@ -402,7 +402,7 @@
if (MO2.getReg()) {
assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
- O << TM.getRegisterInfo()->get(MO2.getReg()).Name;
+ O << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
} else {
O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
@@ -419,7 +419,7 @@
return;
}
- O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
+ O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
if (!MO2.getReg()) {
if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
@@ -432,7 +432,7 @@
O << ", "
<< (char)ARM_AM::getAM2Op(MO3.getImm())
- << TM.getRegisterInfo()->get(MO2.getReg()).Name;
+ << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
O << ", "
@@ -455,7 +455,7 @@
}
O << (char)ARM_AM::getAM2Op(MO2.getImm())
- << TM.getRegisterInfo()->get(MO1.getReg()).Name;
+ << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
O << ", "
@@ -469,12 +469,12 @@
const MachineOperand &MO3 = MI->getOperand(Op+2);
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
- O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
+ O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
if (MO2.getReg()) {
O << ", "
<< (char)ARM_AM::getAM3Op(MO3.getImm())
- << TM.getRegisterInfo()->get(MO2.getReg()).Name
+ << TM.getRegisterInfo()->get(MO2.getReg()).AsmName
<< "]";
return;
}
@@ -492,7 +492,7 @@
if (MO1.getReg()) {
O << (char)ARM_AM::getAM3Op(MO2.getImm())
- << TM.getRegisterInfo()->get(MO1.getReg()).Name;
+ << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
return;
}
@@ -545,13 +545,13 @@
return;
} else if (Modifier && strcmp(Modifier, "base") == 0) {
// Used for FSTM{D|S} and LSTM{D|S} operations.
- O << TM.getRegisterInfo()->get(MO1.getReg()).Name;
+ O << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
if (ARM_AM::getAM5WBFlag(MO2.getImm()))
O << "!";
return;
}
- O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
+ O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
O << ", #"
@@ -570,15 +570,15 @@
const MachineOperand &MO1 = MI->getOperand(Op);
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
- O << "[pc, +" << TM.getRegisterInfo()->get(MO1.getReg()).Name << "]";
+ O << "[pc, +" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName << "]";
}
void
ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
const MachineOperand &MO1 = MI->getOperand(Op);
const MachineOperand &MO2 = MI->getOperand(Op+1);
- O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
- O << ", " << TM.getRegisterInfo()->get(MO2.getReg()).Name << "]";
+ O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
+ O << ", " << TM.getRegisterInfo()->get(MO2.getReg()).AsmName << "]";
}
void
@@ -593,9 +593,9 @@
return;
}
- O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
+ O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
if (MO3.getReg())
- O << ", " << TM.getRegisterInfo()->get(MO3.getReg()).Name;
+ O << ", " << TM.getRegisterInfo()->get(MO3.getReg()).AsmName;
else if (unsigned ImmOffs = MO2.getImm()) {
O << ", #" << ImmOffs;
if (Scale > 1)
@@ -620,7 +620,7 @@
void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
const MachineOperand &MO1 = MI->getOperand(Op);
const MachineOperand &MO2 = MI->getOperand(Op+1);
- O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
+ O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
if (unsigned ImmOffs = MO2.getImm())
O << ", #" << ImmOffs << " * 4";
O << "]";
diff --git a/lib/Target/Alpha/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AlphaAsmPrinter.cpp
index 067a8ef..a46a64c 100644
--- a/lib/Target/Alpha/AlphaAsmPrinter.cpp
+++ b/lib/Target/Alpha/AlphaAsmPrinter.cpp
@@ -77,7 +77,7 @@
if (MO.getType() == MachineOperand::MO_Register) {
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Not physreg??");
- O << TM.getRegisterInfo()->get(MO.getReg()).Name;
+ O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
} else if (MO.isImmediate()) {
O << MO.getImm();
assert(MO.getImm() < (1 << 30));
@@ -92,7 +92,7 @@
switch (MO.getType()) {
case MachineOperand::MO_Register:
- O << RI.get(MO.getReg()).Name;
+ O << RI.get(MO.getReg()).AsmName;
return;
case MachineOperand::MO_Immediate:
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index 3481414..b050deb 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -334,6 +334,6 @@
std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
{
- std::string s(RegisterDescriptors[reg].Name);
+ std::string s(RegisterDescriptors[reg].PrintableName);
return s;
}
diff --git a/lib/Target/CellSPU/SPUAsmPrinter.cpp b/lib/Target/CellSPU/SPUAsmPrinter.cpp
index b62bf62..d96ec9d 100644
--- a/lib/Target/CellSPU/SPUAsmPrinter.cpp
+++ b/lib/Target/CellSPU/SPUAsmPrinter.cpp
@@ -75,14 +75,14 @@
unsigned RegNo = MO.getReg();
assert(TargetRegisterInfo::isPhysicalRegister(RegNo) &&
"Not physreg??");
- O << TM.getRegisterInfo()->get(RegNo).Name;
+ O << TM.getRegisterInfo()->get(RegNo).AsmName;
}
void printOperand(const MachineInstr *MI, unsigned OpNo) {
const MachineOperand &MO = MI->getOperand(OpNo);
if (MO.isRegister()) {
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
- O << TM.getRegisterInfo()->get(MO.getReg()).Name;
+ O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
} else if (MO.isImmediate()) {
O << MO.getImm();
} else {
@@ -149,7 +149,7 @@
// the value contained in the register. For this reason, the darwin
// assembler requires that we print r0 as 0 (no r) when used as the base.
const MachineOperand &MO = MI->getOperand(OpNo);
- O << TM.getRegisterInfo()->get(MO.getReg()).Name;
+ O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
O << ", ";
printOperand(MI, OpNo+1);
}
diff --git a/lib/Target/IA64/IA64AsmPrinter.cpp b/lib/Target/IA64/IA64AsmPrinter.cpp
index 4efc672..264329d 100644
--- a/lib/Target/IA64/IA64AsmPrinter.cpp
+++ b/lib/Target/IA64/IA64AsmPrinter.cpp
@@ -56,7 +56,7 @@
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Not physref??");
//XXX Bug Workaround: See note in Printer::doInitialization about %.
- O << TM.getRegisterInfo()->get(MO.getReg()).Name;
+ O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
} else {
printOp(MO);
}
@@ -168,7 +168,7 @@
const TargetRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_Register:
- O << RI.get(MO.getReg()).Name;
+ O << RI.get(MO.getReg()).AsmName;
return;
case MachineOperand::MO_Immediate:
diff --git a/lib/Target/Mips/MipsAsmPrinter.cpp b/lib/Target/Mips/MipsAsmPrinter.cpp
index 872e51c..4ad57c9 100644
--- a/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -169,9 +169,9 @@
unsigned stackSize = MF.getFrameInfo()->getStackSize();
- O << "\t.frame\t" << "$" << LowercaseString(RI.get(stackReg).Name)
+ O << "\t.frame\t" << "$" << LowercaseString(RI.get(stackReg).AsmName)
<< "," << stackSize << ","
- << "$" << LowercaseString(RI.get(returnReg).Name)
+ << "$" << LowercaseString(RI.get(returnReg).AsmName)
<< "\n";
}
@@ -365,7 +365,7 @@
{
case MachineOperand::MO_Register:
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
- O << "$" << LowercaseString (RI.get(MO.getReg()).Name);
+ O << "$" << LowercaseString (RI.get(MO.getReg()).AsmName);
else
O << "$" << MO.getReg();
break;
diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index acc6570..115e490 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -113,7 +113,7 @@
return;
}
- const char *RegName = TM.getRegisterInfo()->get(RegNo).Name;
+ const char *RegName = TM.getRegisterInfo()->get(RegNo).AsmName;
// Linux assembler (Others?) does not take register mnemonics.
// FIXME - What about special registers used in mfspr/mtspr?
if (!Subtarget.isDarwin()) RegName = stripRegisterPrefix(RegName);
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td
index a64c985..3d55969 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -22,7 +22,7 @@
}
// GP8 - One of the 32 64-bit general-purpose registers
-class GP8<GPR SubReg, string n> : PPCReg<SubReg.Name> {
+class GP8<GPR SubReg, string n> : PPCReg<SubReg.AsmName> {
field bits<5> Num = SubReg.Num;
let SubRegs = [SubReg];
let PrintableName = n;
diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp
index cbbf412..d5b2020 100644
--- a/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -146,7 +146,7 @@
switch (MO.getType()) {
case MachineOperand::MO_Register:
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
- O << "%" << LowercaseString (RI.get(MO.getReg()).Name);
+ O << "%" << LowercaseString (RI.get(MO.getReg()).AsmName);
else
O << "%reg" << MO.getReg();
break;
diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index c430435..47efd5e 100644
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -25,7 +25,7 @@
// in the target machine. String n will become the "name" of the register.
class Register<string n> {
string Namespace = "";
- string Name = n;
+ string AsmName = n;
string PrintableName = n;
// SpillSize - If this value is set to a non-zero value, it is the size in
diff --git a/lib/Target/X86/X86ATTAsmPrinter.cpp b/lib/Target/X86/X86ATTAsmPrinter.cpp
index a6a631b..304e0f7 100644
--- a/lib/Target/X86/X86ATTAsmPrinter.cpp
+++ b/lib/Target/X86/X86ATTAsmPrinter.cpp
@@ -229,7 +229,7 @@
((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);
}
- for (const char *Name = RI.get(Reg).Name; *Name; ++Name)
+ for (const char *Name = RI.get(Reg).AsmName; *Name; ++Name)
O << (char)tolower(*Name);
return;
}
@@ -575,7 +575,7 @@
}
O << '%';
- for (const char *Name = RI.get(Reg).Name; *Name; ++Name)
+ for (const char *Name = RI.get(Reg).AsmName; *Name; ++Name)
O << (char)tolower(*Name);
return false;
}
diff --git a/lib/Target/X86/X86IntelAsmPrinter.cpp b/lib/Target/X86/X86IntelAsmPrinter.cpp
index 64013fc..b753297 100644
--- a/lib/Target/X86/X86IntelAsmPrinter.cpp
+++ b/lib/Target/X86/X86IntelAsmPrinter.cpp
@@ -125,7 +125,7 @@
((strcmp(Modifier,"subreg16") == 0) ? MVT::i16 :MVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);
}
- O << RI.get(Reg).Name;
+ O << RI.get(Reg).AsmName;
} else
O << "reg" << MO.getReg();
return;
@@ -271,7 +271,7 @@
break;
}
- O << '%' << RI.get(Reg).Name;
+ O << '%' << RI.get(Reg).AsmName;
return false;
}
diff --git a/lib/Target/X86/X86IntelAsmPrinter.h b/lib/Target/X86/X86IntelAsmPrinter.h
index 8e7a31c..2a10e1c 100644
--- a/lib/Target/X86/X86IntelAsmPrinter.h
+++ b/lib/Target/X86/X86IntelAsmPrinter.h
@@ -43,7 +43,7 @@
if (MO.isRegister()) {
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Not physreg??");
- O << TM.getRegisterInfo()->get(MO.getReg()).Name;
+ O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
} else {
printOp(MO, Modifier);
}