commit 74d15d36f5ae146853b6089ed4a76a381b11cbb3
author Vikram S. Adve <vadve@cs.uiuc.edu> Wed Jul 02 01:16:01 2003 +0000
committer Vikram S. Adve <vadve@cs.uiuc.edu> Wed Jul 02 01:16:01 2003 +0000
tree 0a1f7c4ca48c25bd645fe04d416499413cbf3cef
parent 784a18b8ba5e3ad2da2fc3503d453f4593f7eaaf

A def. operand of a machine instruction may be an ordinary Value*,
not just an Instruction*, at least in one unfortunate case:
the first operand to the va_arg instruction.
Modify ValueToDefVecMap to map from Value*, not Instruction*.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7052 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/InstrSched/SchedGraph.cpp

diff --git a/lib/CodeGen/InstrSched/SchedGraph.cpp b/lib/CodeGen/InstrSched/SchedGraph.cpp
index 51fca9d..899e188 100644
--- a/lib/CodeGen/InstrSched/SchedGraph.cpp
+++ b/lib/CodeGen/InstrSched/SchedGraph.cpp
@@ -34,9 +34,9 @@
   typedef hash_map<int, RefVec>::const_iterator const_iterator;
 };
 
-struct ValueToDefVecMap: public hash_map<const Instruction*, RefVec> {
-  typedef hash_map<const Instruction*, RefVec>::      iterator       iterator;
-  typedef hash_map<const Instruction*, RefVec>::const_iterator const_iterator;
+struct ValueToDefVecMap: public hash_map<const Value*, RefVec> {
+  typedef hash_map<const Value*, RefVec>::      iterator       iterator;
+  typedef hash_map<const Value*, RefVec>::const_iterator const_iterator;
 };
 
 // 
@@ -636,8 +636,7 @@
     {
     case MachineOperand::MO_VirtualRegister:
     case MachineOperand::MO_CCRegister:
-      if (const Instruction* srcI =
-          dyn_cast_or_null<Instruction>(MI.getOperand(i).getVRegValue()))
+      if (const Value* srcI = MI.getOperand(i).getVRegValue())
       {
         ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
         if (I != valueToDefVecMap.end())
@@ -667,8 +666,7 @@
   // 
   for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i)
     if (MI.getImplicitOp(i).opIsUse() || MI.getImplicitOp(i).opIsDefAndUse())
-      if (const Instruction *srcI =
-          dyn_cast_or_null<Instruction>(MI.getImplicitRef(i)))
+      if (const Value* srcI = MI.getImplicitRef(i))
       {
         ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
         if (I != valueToDefVecMap.end())
@@ -738,9 +736,9 @@
     assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
             mop.getType() == MachineOperand::MO_CCRegister)
            && "Do not expect any other kind of operand to be defined!");
+    assert(mop.getVRegValue() != NULL && "Null value being defined?");
       
-    const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
-    valueToDefVecMap[defInstr].push_back(std::make_pair(node, i)); 
+    valueToDefVecMap[mop.getVRegValue()].push_back(std::make_pair(node, i)); 
   }
   
   // 
@@ -759,10 +757,11 @@
       continue;                     // nothing more to do
     }
 
-    if (mop.opIsDefOnly() || mop.opIsDefAndUse())
-      if (const Instruction* defInstr =
-          dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
-        valueToDefVecMap[defInstr].push_back(std::make_pair(node, -i)); 
+    if (mop.opIsDefOnly() || mop.opIsDefAndUse()) {
+      assert(minstr.getImplicitRef(i) != NULL && "Null value being defined?");
+      valueToDefVecMap[minstr.getImplicitRef(i)].push_back(std::make_pair(node,
+                                                                          -i)); 
+    }
   }
 }