commit 750dbd5950ab5a6689f189adbea900eee9e6884d
author Chris Lattner <sabre@nondot.org> Sat Oct 15 22:35:40 2005 +0000
committer Chris Lattner <sabre@nondot.org> Sat Oct 15 22:35:40 2005 +0000
tree a1245c74b1021b0889a8cac32fd4f8dc0e05b541
parent 85d63bbff740d23fae631ec1ecf5c7603e4b321d

Fix this logic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23756 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 35c981d..5b1d103 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -808,7 +808,7 @@
     if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
       // If the RHS of the AND has zeros where the sign bits of the SRA will
       // land, turn the SRA into an SRL.
-      if (MaskedValueIsZero(N1, (~0ULL << N01C->getValue()) &
+      if (MaskedValueIsZero(N1, (~0ULL << (OpSizeInBits-N01C->getValue())) &
                             (~0ULL>>(64-OpSizeInBits)), TLI)) {
         WorkList.push_back(N);
         CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0),