commit 75361b69f3f327842b9dad69fa7f28ae3b688412
author Chris Lattner <sabre@nondot.org> Wed Apr 07 22:58:41 2010 +0000
committer Chris Lattner <sabre@nondot.org> Wed Apr 07 22:58:41 2010 +0000
tree 5308b9ca3c47b10d83068cbbd7c13bcf8cca7f73
parent e3a601b648e4cbb916e33f969a1b9d3d40b36734

rename llvm::llvm_report_error -> llvm::report_fatal_error



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100709 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/CellSPU/SPUISelLowering.cpp

diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 4b0d442..1a0ab9f 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -75,7 +75,7 @@
       raw_string_ostream Msg(msg);
       Msg << "getValueTypeMapEntry returns NULL for "
            << VT.getEVTString();
-      llvm_report_error(Msg.str());
+      report_fatal_error(Msg.str());
     }
 #endif
 
@@ -719,7 +719,7 @@
       Msg << "LowerLOAD: Got a LoadSDNode with an addr mode other than "
             "UNINDEXED\n";
       Msg << (unsigned) LN->getAddressingMode();
-      llvm_report_error(Msg.str());
+      report_fatal_error(Msg.str());
       /*NOTREACHED*/
     }
   }
@@ -889,7 +889,7 @@
       Msg << "LowerLOAD: Got a LoadSDNode with an addr mode other than "
             "UNINDEXED\n";
       Msg << (unsigned) SN->getAddressingMode();
-      llvm_report_error(Msg.str());
+      report_fatal_error(Msg.str());
       /*NOTREACHED*/
     }
   }
@@ -976,7 +976,7 @@
       return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo);
     }
   } else {
-    llvm_report_error("LowerGlobalAddress: Relocation model other than static"
+    report_fatal_error("LowerGlobalAddress: Relocation model other than static"
                       "not supported.");
     /*NOTREACHED*/
   }
@@ -1043,7 +1043,7 @@
         raw_string_ostream Msg(msg);
         Msg << "LowerFormalArguments Unhandled argument type: "
              << ObjectVT.getEVTString();
-        llvm_report_error(Msg.str());
+        report_fatal_error(Msg.str());
       }
       case MVT::i8:
         ArgRegClass = &SPU::R8CRegClass;
@@ -1586,7 +1586,7 @@
     raw_string_ostream Msg(msg);
     Msg << "CellSPU: Unhandled VT in LowerBUILD_VECTOR, VT = "
          << VT.getEVTString();
-    llvm_report_error(Msg.str());
+    report_fatal_error(Msg.str());
     /*NOTREACHED*/
   }
   case MVT::v4f32: {
@@ -2004,7 +2004,7 @@
     // slot 0 across the vector
     EVT VecVT = N.getValueType();
     if (!VecVT.isSimple() || !VecVT.isVector() || !VecVT.is128BitVector()) {
-      llvm_report_error("LowerEXTRACT_VECTOR_ELT: Must have a simple, 128-bit"
+      report_fatal_error("LowerEXTRACT_VECTOR_ELT: Must have a simple, 128-bit"
                         "vector type!");
     }
 
@@ -2032,7 +2032,7 @@
 
     switch (VT.getSimpleVT().SimpleTy) {
     default:
-      llvm_report_error("LowerEXTRACT_VECTOR_ELT(varable): Unhandled vector"
+      report_fatal_error("LowerEXTRACT_VECTOR_ELT(varable): Unhandled vector"
                         "type");
       /*NOTREACHED*/
     case MVT::i8: {
@@ -2515,7 +2515,7 @@
   case ISD::SETONE:
     compareOp = ISD::SETNE; break;
   default:
-    llvm_report_error("CellSPU ISel Select: unimplemented f64 condition");
+    report_fatal_error("CellSPU ISel Select: unimplemented f64 condition");
   }
 
   SDValue result =