commit 7536eeabf62aefa978898d46fc1915e2c6f56048
author Andrew Lenharth <andrewl@lenharth.org> Sat Feb 12 20:42:09 2005 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Sat Feb 12 20:42:09 2005 +0000
tree 05e7e24a6868b9050f9941e16fafaa1870eb92ff
parent 25e7b16143567846ff95ec723206b0709c785ef6

oops, I was sure this had already gond though the nightly tester


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20141 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaISelPattern.cpp

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 912bb69..49e9b54 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -959,7 +959,7 @@
       case MVT::i1:
         Tmp2 = MakeReg(MVT::i64);
         BuildMI(BB, Alpha::ANDi, 2, Tmp2).addReg(Tmp1).addImm(1);
-        BuildMI(BB, Alpha::SUB, 2, Result).addReg(Alpha::F31).addReg(Tmp2);
+        BuildMI(BB, Alpha::SUBQ, 2, Result).addReg(Alpha::F31).addReg(Tmp2);
         break;
       }
       return Result;