commit 767f8be9eed51f41c8ad03de7684761f82bf26c9
author Bill Wendling <isanbard@gmail.com> Thu Oct 20 20:37:11 2011 +0000
committer Bill Wendling <isanbard@gmail.com> Thu Oct 20 20:37:11 2011 +0000
tree c8e8343d31cca25924eab98600721d41f0157c2e
parent 19595dc4d0cb2495c37828530f04b7e47cf0837f

Add missing operand. <rdar://problem/10313323>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142615 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMISelLowering.cpp

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 34023af..7df743b 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -5924,7 +5924,8 @@
       unsigned VReg1 = MRI->createVirtualRegister(TRC);
       AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
                      .addReg(VReg1, RegState::Define)
-                     .addConstantPoolIndex(Idx));
+                     .addConstantPoolIndex(Idx)
+                     .addImm(0));
       AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
                      .addReg(NewVReg1)
                      .addReg(VReg1, RegState::Kill));