Generalize opcode selection in ARMBaseRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75036 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.h b/lib/Target/ARM/ARMBaseInstrInfo.h
index f263967..9c67c21 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -169,6 +169,7 @@
BR_JTr,
BR_JTm,
BR_JTadd,
+ BX_RET,
FCPYS,
FCPYD,
FLDD,
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 6e24c4e..e51699b 100644
--- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -155,6 +155,11 @@
FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
}
+unsigned ARMBaseRegisterInfo::
+getOpcode(int Op) const {
+ return TII.getOpcode((ARMII::Op)Op);
+}
+
const unsigned*
ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
static const unsigned CalleeSavedRegs[] = {
@@ -878,7 +883,7 @@
void ARMBaseRegisterInfo::
emitLoadConstPool(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
- const TargetInstrInfo *TII, DebugLoc dl,
+ DebugLoc dl,
unsigned DestReg, int Val,
ARMCC::CondCodes Pred,
unsigned PredReg) const {
@@ -887,7 +892,7 @@
Constant *C = ConstantInt::get(Type::Int32Ty, Val);
unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
- BuildMI(MBB, MBBI, dl, TII->get(ARM::LDRcp), DestReg)
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp), DestReg)
.addConstantPoolIndex(Idx)
.addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
}
@@ -923,7 +928,7 @@
MachineBasicBlock::iterator &MBBI,
unsigned DestReg, unsigned BaseReg, int NumBytes,
ARMCC::CondCodes Pred, unsigned PredReg,
- const TargetInstrInfo &TII,
+ const ARMBaseInstrInfo &TII,
DebugLoc dl) {
bool isSub = NumBytes < 0;
if (isSub) NumBytes = -NumBytes;
@@ -941,7 +946,7 @@
assert(SOImmVal != -1 && "Bit extraction didn't work?");
// Build the new ADD / SUB.
- BuildMI(MBB, MBBI, dl, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
+ BuildMI(MBB, MBBI, dl, TII.get(TII.getOpcode(isSub ? ARMII::SUBri : ARMII::ADDri)), DestReg)
.addReg(BaseReg, RegState::Kill).addImm(SOImmVal)
.addImm((unsigned)Pred).addReg(PredReg).addReg(0);
BaseReg = DestReg;
@@ -950,7 +955,7 @@
static void
emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
- const TargetInstrInfo &TII, DebugLoc dl,
+ const ARMBaseInstrInfo &TII, DebugLoc dl,
int NumBytes,
ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
@@ -1050,18 +1055,18 @@
if (Opcode == ARM::INLINEASM)
AddrMode = ARMII::AddrMode2;
- if (Opcode == ARM::ADDri) {
+ if (Opcode == getOpcode(ARMII::ADDri)) {
Offset += MI.getOperand(i+1).getImm();
if (Offset == 0) {
// Turn it into a move.
- MI.setDesc(TII.get(ARM::MOVr));
+ MI.setDesc(TII.get(getOpcode(ARMII::MOVr)));
MI.getOperand(i).ChangeToRegister(FrameReg, false);
MI.RemoveOperand(i+1);
return;
} else if (Offset < 0) {
Offset = -Offset;
isSub = true;
- MI.setDesc(TII.get(ARM::SUBri));
+ MI.setDesc(TII.get(getOpcode(ARMII::SUBri)));
}
// Common case: small offset, fits into instruction.
@@ -1270,13 +1275,13 @@
// Build the new SUBri to adjust SP for integer callee-save spill area 1.
emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS1Size);
- movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
+ movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::STR), 1, STI);
// Darwin ABI requires FP to point to the stack slot that contains the
// previous FP.
if (STI.isTargetDarwin() || hasFP(MF)) {
MachineInstrBuilder MIB =
- BuildMI(MBB, MBBI, dl, TII.get(ARM::ADDri), FramePtr)
+ BuildMI(MBB, MBBI, dl, TII.get(getOpcode(ARMII::ADDri)), FramePtr)
.addFrameIndex(FramePtrSpillFI).addImm(0);
AddDefaultCC(AddDefaultPred(MIB));
}
@@ -1285,7 +1290,7 @@
emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS2Size);
// Build the new SUBri to adjust SP for FP callee-save spill area.
- movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
+ movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::STR), 2, STI);
emitSPUpdate(MBB, MBBI, TII, dl, -DPRCSSize);
// Determine starting offsets of spill areas.
@@ -1300,7 +1305,7 @@
NumBytes = DPRCSOffset;
if (NumBytes) {
// Insert it after all the callee-save spills.
- movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
+ movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::FSTD), 3, STI);
emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes);
}
@@ -1321,9 +1326,11 @@
return false;
}
-static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
- return ((MI->getOpcode() == ARM::FLDD ||
- MI->getOpcode() == ARM::LDR) &&
+static bool isCSRestore(MachineInstr *MI,
+ const ARMBaseInstrInfo &TII,
+ const unsigned *CSRegs) {
+ return ((MI->getOpcode() == (int)TII.getOpcode(ARMII::FLDD) ||
+ MI->getOpcode() == (int)TII.getOpcode(ARMII::LDR)) &&
MI->getOperand(1).isFI() &&
isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
}
@@ -1332,7 +1339,7 @@
emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = prior(MBB.end());
- assert(MBBI->getOpcode() == ARM::BX_RET &&
+ assert(MBBI->getOpcode() == (int)getOpcode(ARMII::BX_RET) &&
"Can only insert epilog into returning blocks");
DebugLoc dl = MBBI->getDebugLoc();
MachineFrameInfo *MFI = MF.getFrameInfo();
@@ -1349,8 +1356,8 @@
if (MBBI != MBB.begin()) {
do
--MBBI;
- while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
- if (!isCSRestore(MBBI, CSRegs))
+ while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
+ if (!isCSRestore(MBBI, TII, CSRegs))
++MBBI;
}
@@ -1370,11 +1377,11 @@
AFI->getDPRCalleeSavedAreaOffset()||
hasFP(MF)) {
if (NumBytes)
- BuildMI(MBB, MBBI, dl, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
+ BuildMI(MBB, MBBI, dl, TII.get(getOpcode(ARMII::SUBri)), ARM::SP).addReg(FramePtr)
.addImm(NumBytes)
.addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
else
- BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
+ BuildMI(MBB, MBBI, dl, TII.get(getOpcode(ARMII::MOVr)), ARM::SP).addReg(FramePtr)
.addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
}
} else if (NumBytes) {
@@ -1382,15 +1389,15 @@
}
// Move SP to start of integer callee save spill area 2.
- movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
+ movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::FLDD), 3, STI);
emitSPUpdate(MBB, MBBI, TII, dl, AFI->getDPRCalleeSavedAreaSize());
// Move SP to start of integer callee save spill area 1.
- movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
+ movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::LDR), 2, STI);
emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea2Size());
// Move SP to SP upon entry to the function.
- movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
+ movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::LDR), 1, STI);
emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea1Size());
}
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.h b/lib/Target/ARM/ARMBaseRegisterInfo.h
index d745970..eedb79e 100644
--- a/lib/Target/ARM/ARMBaseRegisterInfo.h
+++ b/lib/Target/ARM/ARMBaseRegisterInfo.h
@@ -55,6 +55,9 @@
// Can be only subclassed.
explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
+ // Return the opcode that implements 'Op', or 0 if no opcode
+ unsigned getOpcode(int Op) const;
+
public:
/// getRegisterNumbering - Given the enum value for some register, e.g.
/// ARM::LR, return the number that it corresponds to (e.g. 14).
@@ -107,7 +110,7 @@
/// specified immediate.
virtual void emitLoadConstPool(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
- const TargetInstrInfo *TII, DebugLoc dl,
+ DebugLoc dl,
unsigned DestReg, int Val,
ARMCC::CondCodes Pred = ARMCC::AL,
unsigned PredReg = 0) const;
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 0aaa311..ab0a391 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -73,6 +73,7 @@
case ARMII::BR_JTr: return ARM::BR_JTr;
case ARMII::BR_JTm: return ARM::BR_JTm;
case ARMII::BR_JTadd: return ARM::BR_JTadd;
+ case ARMII::BX_RET: return ARM::BX_RET;
case ARMII::FCPYS: return ARM::FCPYS;
case ARMII::FCPYD: return ARM::FCPYD;
case ARMII::FLDD: return ARM::FLDD;
@@ -120,7 +121,7 @@
const MachineInstr *Orig) const {
DebugLoc dl = Orig->getDebugLoc();
if (Orig->getOpcode() == ARM::MOVi2pieces) {
- RI.emitLoadConstPool(MBB, I, this, dl,
+ RI.emitLoadConstPool(MBB, I, dl,
DestReg,
Orig->getOperand(1).getImm(),
(ARMCC::CondCodes)Orig->getOperand(2).getImm(),
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 65d90b6..330c7a9 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -1063,34 +1063,34 @@
// Control-Flow Instructions
//
-//let isReturn = 1, isTerminator = 1 in
-// def t2BX_RET : T2XI<(outs), (ins), "bx lr", [(ARMretflag)]>;
-//
+let isReturn = 1, isTerminator = 1 in
+ def t2BX_RET : T2XI<(outs), (ins), "bx lr", [(ARMretflag)]>;
+
// On non-Darwin platforms R9 is callee-saved.
-//let isCall = 1,
-// Defs = [R0, R1, R2, R3, R12, LR,
-// D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
-//def t2BL : T2XI<(outs), (ins i32imm:$func, variable_ops),
-// "bl ${func:call}",
-// [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
-//
-//def t2BLX : T2XI<(outs), (ins GPR:$func, variable_ops),
-// "blx $func",
-// [(ARMcall GPR:$func)]>, Requires<[IsNotDarwin]>;
-//}
+let isCall = 1,
+ Defs = [R0, R1, R2, R3, R12, LR,
+ D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
+def t2BL : T2XI<(outs), (ins i32imm:$func, variable_ops),
+ "bl ${func:call}",
+ [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
+
+def t2BLX : T2XI<(outs), (ins GPR:$func, variable_ops),
+ "blx $func",
+ [(ARMcall GPR:$func)]>, Requires<[IsNotDarwin]>;
+}
// On Darwin R9 is call-clobbered.
-//let isCall = 1,
-// Defs = [R0, R1, R2, R3, R9, R12, LR,
-// D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
-//def t2BLr9 : T2XI<(outs), (ins i32imm:$func, variable_ops),
-// "bl ${func:call}",
-// [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>;
-//
-//def t2BLXr9 : T2XI<(outs), (ins GPR:$func, variable_ops),
-// "blx $func",
-// [(ARMcall GPR:$func)]>, Requires<[IsDarwin]>;
-//}
+let isCall = 1,
+ Defs = [R0, R1, R2, R3, R9, R12, LR,
+ D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
+def t2BLr9 : T2XI<(outs), (ins i32imm:$func, variable_ops),
+ "bl ${func:call}",
+ [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>;
+
+def t2BLXr9 : T2XI<(outs), (ins GPR:$func, variable_ops),
+ "blx $func",
+ [(ARMcall GPR:$func)]>, Requires<[IsDarwin]>;
+}
let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
let isPredicable = 1 in
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index cf5f336..d5bc3f6 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -13,6 +13,7 @@
#include "ARM.h"
#include "ARMAddressingModes.h"
+#include "ARMBaseInstrInfo.h"
#include "ARMInstrInfo.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMRegisterInfo.h"
diff --git a/lib/Target/ARM/Thumb1InstrInfo.cpp b/lib/Target/ARM/Thumb1InstrInfo.cpp
index 6cdc718..e2f2c5d 100644
--- a/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -42,6 +42,7 @@
case ARMII::BR_JTr: return ARM::tBR_JTr;
case ARMII::BR_JTm: return 0;
case ARMII::BR_JTadd: return 0;
+ case ARMII::BX_RET: return ARM::tBX_RET;
case ARMII::FCPYS: return 0;
case ARMII::FCPYD: return 0;
case ARMII::FLDD: return 0;
diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp
index cd77a75..316f5ad 100644
--- a/lib/Target/ARM/Thumb1RegisterInfo.cpp
+++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp
@@ -13,6 +13,7 @@
#include "ARM.h"
#include "ARMAddressingModes.h"
+#include "ARMBaseInstrInfo.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMSubtarget.h"
#include "Thumb1InstrInfo.h"
@@ -47,7 +48,7 @@
/// specified immediate.
void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
- const TargetInstrInfo *TII, DebugLoc dl,
+ DebugLoc dl,
unsigned DestReg, int Val,
ARMCC::CondCodes Pred,
unsigned PredReg) const {
@@ -56,7 +57,7 @@
Constant *C = ConstantInt::get(Type::Int32Ty, Val);
unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
- BuildMI(MBB, MBBI, dl, TII->get(ARM::tLDRcp), DestReg)
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp), DestReg)
.addConstantPoolIndex(Idx);
}
@@ -131,7 +132,7 @@
BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg)
.addReg(LdReg, RegState::Kill);
} else
- MRI.emitLoadConstPool(MBB, MBBI, &TII, dl, LdReg, NumBytes);
+ MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, NumBytes);
// Emit add / sub.
int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
@@ -505,7 +506,7 @@
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
Offset, false, TII, *this, dl);
else {
- emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset);
+ emitLoadConstPool(MBB, II, dl, TmpReg, Offset);
UseRR = true;
}
} else
@@ -543,7 +544,7 @@
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
Offset, false, TII, *this, dl);
else {
- emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset);
+ emitLoadConstPool(MBB, II, dl, TmpReg, Offset);
UseRR = true;
}
} else
diff --git a/lib/Target/ARM/Thumb1RegisterInfo.h b/lib/Target/ARM/Thumb1RegisterInfo.h
index 28a5046..6e8dd3d 100644
--- a/lib/Target/ARM/Thumb1RegisterInfo.h
+++ b/lib/Target/ARM/Thumb1RegisterInfo.h
@@ -31,7 +31,7 @@
/// specified immediate.
void emitLoadConstPool(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
- const TargetInstrInfo *TII, DebugLoc dl,
+ DebugLoc dl,
unsigned DestReg, int Val,
ARMCC::CondCodes Pred = ARMCC::AL,
unsigned PredReg = 0) const;
diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp
index 94c065e..76fc4fb 100644
--- a/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -43,6 +43,7 @@
case ARMII::BR_JTr: return ARM::t2BR_JTr;
case ARMII::BR_JTm: return ARM::t2BR_JTm;
case ARMII::BR_JTadd: return ARM::t2BR_JTadd;
+ case ARMII::BX_RET: return ARM::t2BX_RET;
case ARMII::FCPYS: return ARM::FCPYS;
case ARMII::FCPYD: return ARM::FCPYD;
case ARMII::FLDD: return ARM::FLDD;
diff --git a/lib/Target/ARM/Thumb2RegisterInfo.cpp b/lib/Target/ARM/Thumb2RegisterInfo.cpp
index c1326e6..bca205a 100644
--- a/lib/Target/ARM/Thumb2RegisterInfo.cpp
+++ b/lib/Target/ARM/Thumb2RegisterInfo.cpp
@@ -13,6 +13,7 @@
#include "ARM.h"
#include "ARMAddressingModes.h"
+#include "ARMBaseInstrInfo.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMSubtarget.h"
#include "Thumb2InstrInfo.h"
@@ -47,7 +48,7 @@
/// specified immediate.
void Thumb2RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
- const TargetInstrInfo *TII, DebugLoc dl,
+ DebugLoc dl,
unsigned DestReg, int Val,
ARMCC::CondCodes Pred,
unsigned PredReg) const {
@@ -56,8 +57,8 @@
Constant *C = ConstantInt::get(Type::Int32Ty, Val);
unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
- BuildMI(MBB, MBBI, dl, TII->get(ARM::tLDRcp), DestReg)
- .addConstantPoolIndex(Idx);
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci), DestReg)
+ .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
}
const TargetRegisterClass*
@@ -131,7 +132,7 @@
BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg)
.addReg(LdReg, RegState::Kill);
} else
- MRI.emitLoadConstPool(MBB, MBBI, &TII, dl, LdReg, NumBytes);
+ MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, NumBytes);
// Emit add / sub.
int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
@@ -505,7 +506,7 @@
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
Offset, false, TII, *this, dl);
else {
- emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset);
+ emitLoadConstPool(MBB, II, dl, TmpReg, Offset);
UseRR = true;
}
} else
@@ -543,7 +544,7 @@
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
Offset, false, TII, *this, dl);
else {
- emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset);
+ emitLoadConstPool(MBB, II, dl, TmpReg, Offset);
UseRR = true;
}
} else
diff --git a/lib/Target/ARM/Thumb2RegisterInfo.h b/lib/Target/ARM/Thumb2RegisterInfo.h
index 15faa1c..c363516 100644
--- a/lib/Target/ARM/Thumb2RegisterInfo.h
+++ b/lib/Target/ARM/Thumb2RegisterInfo.h
@@ -31,7 +31,7 @@
/// specified immediate.
void emitLoadConstPool(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
- const TargetInstrInfo *TII, DebugLoc dl,
+ DebugLoc dl,
unsigned DestReg, int Val,
ARMCC::CondCodes Pred = ARMCC::AL,
unsigned PredReg = 0) const;