Generalize opcode selection in ARMBaseRegisterInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75036 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/Thumb1InstrInfo.cpp b/lib/Target/ARM/Thumb1InstrInfo.cpp
index 6cdc718..e2f2c5d 100644
--- a/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -42,6 +42,7 @@
   case ARMII::BR_JTr: return ARM::tBR_JTr;
   case ARMII::BR_JTm: return 0;
   case ARMII::BR_JTadd: return 0;
+  case ARMII::BX_RET: return ARM::tBX_RET;
   case ARMII::FCPYS: return 0;
   case ARMII::FCPYD: return 0;
   case ARMII::FLDD: return 0;