Add intrinsics for log, log2, log10, exp, exp2.
No functional change (and no FE change to generate them).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55753 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/IntrinsicLowering.cpp b/lib/CodeGen/IntrinsicLowering.cpp
index bd3c8c7..6f9c4af 100644
--- a/lib/CodeGen/IntrinsicLowering.cpp
+++ b/lib/CodeGen/IntrinsicLowering.cpp
@@ -160,6 +160,81 @@
I->arg_begin()->getType());
}
break;
+ case Intrinsic::log:
+ switch((int)I->arg_begin()->getType()->getTypeID()) {
+ case Type::FloatTyID:
+ EnsureFunctionExists(M, "logf", I->arg_begin(), I->arg_end(),
+ Type::FloatTy);
+ case Type::DoubleTyID:
+ EnsureFunctionExists(M, "log", I->arg_begin(), I->arg_end(),
+ Type::DoubleTy);
+ case Type::X86_FP80TyID:
+ case Type::FP128TyID:
+ case Type::PPC_FP128TyID:
+ EnsureFunctionExists(M, "logl", I->arg_begin(), I->arg_end(),
+ I->arg_begin()->getType());
+ }
+ break;
+ case Intrinsic::log2:
+ switch((int)I->arg_begin()->getType()->getTypeID()) {
+ case Type::FloatTyID:
+ EnsureFunctionExists(M, "log2f", I->arg_begin(), I->arg_end(),
+ Type::FloatTy);
+ case Type::DoubleTyID:
+ EnsureFunctionExists(M, "log2", I->arg_begin(), I->arg_end(),
+ Type::DoubleTy);
+ case Type::X86_FP80TyID:
+ case Type::FP128TyID:
+ case Type::PPC_FP128TyID:
+ EnsureFunctionExists(M, "log2l", I->arg_begin(), I->arg_end(),
+ I->arg_begin()->getType());
+ }
+ break;
+ case Intrinsic::log10:
+ switch((int)I->arg_begin()->getType()->getTypeID()) {
+ case Type::FloatTyID:
+ EnsureFunctionExists(M, "log10f", I->arg_begin(), I->arg_end(),
+ Type::FloatTy);
+ case Type::DoubleTyID:
+ EnsureFunctionExists(M, "log10", I->arg_begin(), I->arg_end(),
+ Type::DoubleTy);
+ case Type::X86_FP80TyID:
+ case Type::FP128TyID:
+ case Type::PPC_FP128TyID:
+ EnsureFunctionExists(M, "log10l", I->arg_begin(), I->arg_end(),
+ I->arg_begin()->getType());
+ }
+ break;
+ case Intrinsic::exp:
+ switch((int)I->arg_begin()->getType()->getTypeID()) {
+ case Type::FloatTyID:
+ EnsureFunctionExists(M, "expf", I->arg_begin(), I->arg_end(),
+ Type::FloatTy);
+ case Type::DoubleTyID:
+ EnsureFunctionExists(M, "exp", I->arg_begin(), I->arg_end(),
+ Type::DoubleTy);
+ case Type::X86_FP80TyID:
+ case Type::FP128TyID:
+ case Type::PPC_FP128TyID:
+ EnsureFunctionExists(M, "expl", I->arg_begin(), I->arg_end(),
+ I->arg_begin()->getType());
+ }
+ break;
+ case Intrinsic::exp2:
+ switch((int)I->arg_begin()->getType()->getTypeID()) {
+ case Type::FloatTyID:
+ EnsureFunctionExists(M, "exp2f", I->arg_begin(), I->arg_end(),
+ Type::FloatTy);
+ case Type::DoubleTyID:
+ EnsureFunctionExists(M, "exp2", I->arg_begin(), I->arg_end(),
+ Type::DoubleTy);
+ case Type::X86_FP80TyID:
+ case Type::FP128TyID:
+ case Type::PPC_FP128TyID:
+ EnsureFunctionExists(M, "exp2l", I->arg_begin(), I->arg_end(),
+ I->arg_begin()->getType());
+ }
+ break;
}
}
@@ -857,6 +932,144 @@
}
break;
}
+ case Intrinsic::log: {
+ static Constant *logfFCache = 0;
+ static Constant *logFCache = 0;
+ static Constant *logLDCache = 0;
+ switch (CI->getOperand(1)->getType()->getTypeID()) {
+ default: assert(0 && "Invalid type in log"); abort();
+ case Type::FloatTyID:
+ ReplaceCallWith("logf", CI, CI->op_begin()+1, CI->op_end(),
+ Type::FloatTy, logfFCache);
+ break;
+ case Type::DoubleTyID:
+ ReplaceCallWith("log", CI, CI->op_begin()+1, CI->op_end(),
+ Type::DoubleTy, logFCache);
+ break;
+ case Type::X86_FP80TyID:
+ case Type::FP128TyID:
+ case Type::PPC_FP128TyID:
+ ReplaceCallWith("logl", CI, CI->op_begin()+1, CI->op_end(),
+ CI->getOperand(1)->getType(), logLDCache);
+ break;
+ }
+ break;
+ }
+ case Intrinsic::log2: {
+ static Constant *log2fFCache = 0;
+ static Constant *log2FCache = 0;
+ static Constant *log2LDCache = 0;
+ switch (CI->getOperand(1)->getType()->getTypeID()) {
+ default: assert(0 && "Invalid type in log2"); abort();
+ case Type::FloatTyID:
+ ReplaceCallWith("log2f", CI, CI->op_begin()+1, CI->op_end(),
+ Type::FloatTy, log2fFCache);
+ break;
+ case Type::DoubleTyID:
+ ReplaceCallWith("log2", CI, CI->op_begin()+1, CI->op_end(),
+ Type::DoubleTy, log2FCache);
+ break;
+ case Type::X86_FP80TyID:
+ case Type::FP128TyID:
+ case Type::PPC_FP128TyID:
+ ReplaceCallWith("log2l", CI, CI->op_begin()+1, CI->op_end(),
+ CI->getOperand(1)->getType(), log2LDCache);
+ break;
+ }
+ break;
+ }
+ case Intrinsic::log10: {
+ static Constant *log10fFCache = 0;
+ static Constant *log10FCache = 0;
+ static Constant *log10LDCache = 0;
+ switch (CI->getOperand(1)->getType()->getTypeID()) {
+ default: assert(0 && "Invalid type in log10"); abort();
+ case Type::FloatTyID:
+ ReplaceCallWith("log10f", CI, CI->op_begin()+1, CI->op_end(),
+ Type::FloatTy, log10fFCache);
+ break;
+ case Type::DoubleTyID:
+ ReplaceCallWith("log10", CI, CI->op_begin()+1, CI->op_end(),
+ Type::DoubleTy, log10FCache);
+ break;
+ case Type::X86_FP80TyID:
+ case Type::FP128TyID:
+ case Type::PPC_FP128TyID:
+ ReplaceCallWith("log10l", CI, CI->op_begin()+1, CI->op_end(),
+ CI->getOperand(1)->getType(), log10LDCache);
+ break;
+ }
+ break;
+ }
+ case Intrinsic::exp: {
+ static Constant *expfFCache = 0;
+ static Constant *expFCache = 0;
+ static Constant *expLDCache = 0;
+ switch (CI->getOperand(1)->getType()->getTypeID()) {
+ default: assert(0 && "Invalid type in exp"); abort();
+ case Type::FloatTyID:
+ ReplaceCallWith("expf", CI, CI->op_begin()+1, CI->op_end(),
+ Type::FloatTy, expfFCache);
+ break;
+ case Type::DoubleTyID:
+ ReplaceCallWith("exp", CI, CI->op_begin()+1, CI->op_end(),
+ Type::DoubleTy, expFCache);
+ break;
+ case Type::X86_FP80TyID:
+ case Type::FP128TyID:
+ case Type::PPC_FP128TyID:
+ ReplaceCallWith("expl", CI, CI->op_begin()+1, CI->op_end(),
+ CI->getOperand(1)->getType(), expLDCache);
+ break;
+ }
+ break;
+ }
+ case Intrinsic::exp2: {
+ static Constant *exp2fFCache = 0;
+ static Constant *exp2FCache = 0;
+ static Constant *exp2LDCache = 0;
+ switch (CI->getOperand(1)->getType()->getTypeID()) {
+ default: assert(0 && "Invalid type in exp2"); abort();
+ case Type::FloatTyID:
+ ReplaceCallWith("exp2f", CI, CI->op_begin()+1, CI->op_end(),
+ Type::FloatTy, exp2fFCache);
+ break;
+ case Type::DoubleTyID:
+ ReplaceCallWith("exp2", CI, CI->op_begin()+1, CI->op_end(),
+ Type::DoubleTy, exp2FCache);
+ break;
+ case Type::X86_FP80TyID:
+ case Type::FP128TyID:
+ case Type::PPC_FP128TyID:
+ ReplaceCallWith("exp2l", CI, CI->op_begin()+1, CI->op_end(),
+ CI->getOperand(1)->getType(), exp2LDCache);
+ break;
+ }
+ break;
+ }
+ case Intrinsic::pow: {
+ static Constant *powfFCache = 0;
+ static Constant *powFCache = 0;
+ static Constant *powLDCache = 0;
+ switch (CI->getOperand(1)->getType()->getTypeID()) {
+ default: assert(0 && "Invalid type in pow"); abort();
+ case Type::FloatTyID:
+ ReplaceCallWith("powf", CI, CI->op_begin()+1, CI->op_end(),
+ Type::FloatTy, powfFCache);
+ break;
+ case Type::DoubleTyID:
+ ReplaceCallWith("pow", CI, CI->op_begin()+1, CI->op_end(),
+ Type::DoubleTy, powFCache);
+ break;
+ case Type::X86_FP80TyID:
+ case Type::FP128TyID:
+ case Type::PPC_FP128TyID:
+ ReplaceCallWith("powl", CI, CI->op_begin()+1, CI->op_end(),
+ CI->getOperand(1)->getType(), powLDCache);
+ break;
+ }
+ break;
+ }
case Intrinsic::flt_rounds:
// Lower to "round to the nearest"
if (CI->getType() != Type::VoidTy)
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 8b20052..1155add 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3490,6 +3490,11 @@
case ISD::FSQRT:
case ISD::FSIN:
case ISD::FCOS:
+ case ISD::FLOG:
+ case ISD::FLOG2:
+ case ISD::FLOG10:
+ case ISD::FEXP:
+ case ISD::FEXP2:
case ISD::FTRUNC:
case ISD::FFLOOR:
case ISD::FCEIL:
@@ -3526,6 +3531,11 @@
Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
break;
}
+ case ISD::FLOG:
+ case ISD::FLOG2:
+ case ISD::FLOG10:
+ case ISD::FEXP:
+ case ISD::FEXP2:
case ISD::FTRUNC:
case ISD::FFLOOR:
case ISD::FCEIL:
@@ -3556,6 +3566,26 @@
LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
RTLIB::COS_F80, RTLIB::COS_PPCF128);
break;
+ case ISD::FLOG:
+ LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
+ RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
+ break;
+ case ISD::FLOG2:
+ LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
+ RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
+ break;
+ case ISD::FLOG10:
+ LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
+ RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
+ break;
+ case ISD::FEXP:
+ LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
+ RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
+ break;
+ case ISD::FEXP2:
+ LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
+ RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
+ break;
case ISD::FTRUNC:
LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
@@ -4163,6 +4193,11 @@
// precision, and these operations don't modify precision at all.
break;
+ case ISD::FLOG:
+ case ISD::FLOG2:
+ case ISD::FLOG10:
+ case ISD::FEXP:
+ case ISD::FEXP2:
case ISD::FSQRT:
case ISD::FSIN:
case ISD::FCOS:
@@ -6574,6 +6609,11 @@
RTLIB::POWI_PPCF128),
Node, false, Hi);
break;
+ case ISD::FLOG:
+ case ISD::FLOG2:
+ case ISD::FLOG10:
+ case ISD::FEXP:
+ case ISD::FEXP2:
case ISD::FTRUNC:
case ISD::FFLOOR:
case ISD::FCEIL:
@@ -6596,6 +6636,26 @@
LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
RTLIB::COS_F80, RTLIB::COS_PPCF128);
break;
+ case ISD::FLOG:
+ LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
+ RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
+ break;
+ case ISD::FLOG2:
+ LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
+ RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
+ break;
+ case ISD::FLOG10:
+ LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
+ RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
+ break;
+ case ISD::FEXP:
+ LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
+ RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
+ break;
+ case ISD::FEXP2:
+ LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
+ RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
+ break;
case ISD::FTRUNC:
LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
@@ -6966,6 +7026,11 @@
case ISD::FSQRT:
case ISD::FSIN:
case ISD::FCOS:
+ case ISD::FLOG:
+ case ISD::FLOG2:
+ case ISD::FLOG10:
+ case ISD::FEXP:
+ case ISD::FEXP2:
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT:
case ISD::SINT_TO_FP:
@@ -7102,6 +7167,11 @@
case ISD::FSQRT:
case ISD::FSIN:
case ISD::FCOS:
+ case ISD::FLOG:
+ case ISD::FLOG2:
+ case ISD::FLOG10:
+ case ISD::FEXP:
+ case ISD::FEXP2:
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT:
case ISD::SINT_TO_FP:
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index 70bf549..e962368 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -3015,6 +3015,31 @@
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
return 0;
+ case Intrinsic::log:
+ setValue(&I, DAG.getNode(ISD::FLOG,
+ getValue(I.getOperand(1)).getValueType(),
+ getValue(I.getOperand(1))));
+ return 0;
+ case Intrinsic::log2:
+ setValue(&I, DAG.getNode(ISD::FLOG2,
+ getValue(I.getOperand(1)).getValueType(),
+ getValue(I.getOperand(1))));
+ return 0;
+ case Intrinsic::log10:
+ setValue(&I, DAG.getNode(ISD::FLOG10,
+ getValue(I.getOperand(1)).getValueType(),
+ getValue(I.getOperand(1))));
+ return 0;
+ case Intrinsic::exp:
+ setValue(&I, DAG.getNode(ISD::FEXP,
+ getValue(I.getOperand(1)).getValueType(),
+ getValue(I.getOperand(1))));
+ return 0;
+ case Intrinsic::exp2:
+ setValue(&I, DAG.getNode(ISD::FEXP2,
+ getValue(I.getOperand(1)).getValueType(),
+ getValue(I.getOperand(1))));
+ return 0;
case Intrinsic::pow:
setValue(&I, DAG.getNode(ISD::FPOW,
getValue(I.getOperand(1)).getValueType(),
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 6a2f91f..ff48ba2 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -83,6 +83,26 @@
Names[RTLIB::SQRT_F64] = "sqrt";
Names[RTLIB::SQRT_F80] = "sqrtl";
Names[RTLIB::SQRT_PPCF128] = "sqrtl";
+ Names[RTLIB::LOG_F32] = "logf";
+ Names[RTLIB::LOG_F64] = "log";
+ Names[RTLIB::LOG_F80] = "logl";
+ Names[RTLIB::LOG_PPCF128] = "logl";
+ Names[RTLIB::LOG2_F32] = "log2f";
+ Names[RTLIB::LOG2_F64] = "log2";
+ Names[RTLIB::LOG2_F80] = "log2l";
+ Names[RTLIB::LOG2_PPCF128] = "log2l";
+ Names[RTLIB::LOG10_F32] = "log10f";
+ Names[RTLIB::LOG10_F64] = "log10";
+ Names[RTLIB::LOG10_F80] = "log10l";
+ Names[RTLIB::LOG10_PPCF128] = "log10l";
+ Names[RTLIB::EXP_F32] = "expf";
+ Names[RTLIB::EXP_F64] = "exp";
+ Names[RTLIB::EXP_F80] = "expl";
+ Names[RTLIB::EXP_PPCF128] = "expl";
+ Names[RTLIB::EXP2_F32] = "exp2f";
+ Names[RTLIB::EXP2_F64] = "exp2";
+ Names[RTLIB::EXP2_F80] = "exp2l";
+ Names[RTLIB::EXP2_PPCF128] = "exp2l";
Names[RTLIB::SIN_F32] = "sinf";
Names[RTLIB::SIN_F64] = "sin";
Names[RTLIB::SIN_F80] = "sinl";
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index b827a23..a984c18 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -243,6 +243,16 @@
setOperationAction(ISD::FCOS , MVT::f64, Expand);
setOperationAction(ISD::FREM , MVT::f64, Expand);
setOperationAction(ISD::FREM , MVT::f32, Expand);
+ setOperationAction(ISD::FLOG , MVT::f64, Expand);
+ setOperationAction(ISD::FLOG , MVT::f32, Expand);
+ setOperationAction(ISD::FLOG2 , MVT::f64, Expand);
+ setOperationAction(ISD::FLOG2 , MVT::f32, Expand);
+ setOperationAction(ISD::FLOG10 , MVT::f64, Expand);
+ setOperationAction(ISD::FLOG10 , MVT::f32, Expand);
+ setOperationAction(ISD::FEXP , MVT::f64, Expand);
+ setOperationAction(ISD::FEXP , MVT::f32, Expand);
+ setOperationAction(ISD::FEXP2 , MVT::f64, Expand);
+ setOperationAction(ISD::FEXP2 , MVT::f32, Expand);
if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 7beea3b..3de571c 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -98,6 +98,17 @@
setOperationAction(ISD::FPOW , MVT::f32, Expand);
setOperationAction(ISD::FPOW , MVT::f64, Expand);
+
+ setOperationAction(ISD::FLOG, MVT::f32, Expand);
+ setOperationAction(ISD::FLOG, MVT::f64, Expand);
+ setOperationAction(ISD::FLOG2, MVT::f32, Expand);
+ setOperationAction(ISD::FLOG2, MVT::f64, Expand);
+ setOperationAction(ISD::FLOG10, MVT::f32, Expand);
+ setOperationAction(ISD::FLOG10, MVT::f64, Expand);
+ setOperationAction(ISD::FEXP, MVT::f32, Expand);
+ setOperationAction(ISD::FEXP, MVT::f64, Expand);
+ setOperationAction(ISD::FEXP2, MVT::f32, Expand);
+ setOperationAction(ISD::FEXP2, MVT::f64, Expand);
setOperationAction(ISD::SETCC, MVT::f32, Promote);
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index b272b4b..3009143 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -189,9 +189,19 @@
setOperationAction(ISD::FSIN , MVT::f64, Expand);
setOperationAction(ISD::FCOS , MVT::f64, Expand);
setOperationAction(ISD::FREM , MVT::f64, Expand);
+ setOperationAction(ISD::FLOG , MVT::f64, Expand);
+ setOperationAction(ISD::FLOG2, MVT::f64, Expand);
+ setOperationAction(ISD::FLOG10,MVT::f64, Expand);
+ setOperationAction(ISD::FEXP , MVT::f64, Expand);
+ setOperationAction(ISD::FEXP2, MVT::f64, Expand);
setOperationAction(ISD::FSIN , MVT::f32, Expand);
setOperationAction(ISD::FCOS , MVT::f32, Expand);
setOperationAction(ISD::FREM , MVT::f32, Expand);
+ setOperationAction(ISD::FLOG , MVT::f32, Expand);
+ setOperationAction(ISD::FLOG2, MVT::f32, Expand);
+ setOperationAction(ISD::FLOG10,MVT::f32, Expand);
+ setOperationAction(ISD::FEXP , MVT::f32, Expand);
+ setOperationAction(ISD::FEXP2, MVT::f32, Expand);
// If we're enabling GP optimizations, use hardware square root
setOperationAction(ISD::FSQRT, MVT::f64, Expand);
diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index 9cd9ef0..cdcacf3 100644
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -75,10 +75,20 @@
setOperationAction(ISD::FCOS , MVT::f64, Expand);
setOperationAction(ISD::FSQRT, MVT::f64, Expand);
setOperationAction(ISD::FPOW , MVT::f64, Expand);
+ setOperationAction(ISD::FLOG , MVT::f64, Expand);
+ setOperationAction(ISD::FLOG2, MVT::f64, Expand);
+ setOperationAction(ISD::FLOG10,MVT::f64, Expand);
+ setOperationAction(ISD::FEXP , MVT::f64, Expand);
+ setOperationAction(ISD::FEXP2, MVT::f64, Expand);
setOperationAction(ISD::FSIN , MVT::f32, Expand);
setOperationAction(ISD::FCOS , MVT::f32, Expand);
setOperationAction(ISD::FSQRT, MVT::f32, Expand);
setOperationAction(ISD::FPOW , MVT::f32, Expand);
+ setOperationAction(ISD::FLOG , MVT::f32, Expand);
+ setOperationAction(ISD::FLOG2, MVT::f32, Expand);
+ setOperationAction(ISD::FLOG10,MVT::f32, Expand);
+ setOperationAction(ISD::FEXP , MVT::f32, Expand);
+ setOperationAction(ISD::FEXP2, MVT::f32, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 3fb4263..e508b0b 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -99,10 +99,20 @@
setOperationAction(ISD::FCOS , MVT::f64, Expand);
setOperationAction(ISD::FREM , MVT::f64, Expand);
setOperationAction(ISD::FPOW , MVT::f64, Expand);
+ setOperationAction(ISD::FLOG , MVT::f64, Expand);
+ setOperationAction(ISD::FLOG2, MVT::f64, Expand);
+ setOperationAction(ISD::FLOG10,MVT::f64, Expand);
+ setOperationAction(ISD::FEXP ,MVT::f64, Expand);
+ setOperationAction(ISD::FEXP2 ,MVT::f64, Expand);
setOperationAction(ISD::FSIN , MVT::f32, Expand);
setOperationAction(ISD::FCOS , MVT::f32, Expand);
setOperationAction(ISD::FREM , MVT::f32, Expand);
setOperationAction(ISD::FPOW , MVT::f32, Expand);
+ setOperationAction(ISD::FLOG , MVT::f32, Expand);
+ setOperationAction(ISD::FLOG2 ,MVT::f32, Expand);
+ setOperationAction(ISD::FLOG10,MVT::f32, Expand);
+ setOperationAction(ISD::FEXP ,MVT::f32, Expand);
+ setOperationAction(ISD::FEXP2 ,MVT::f32, Expand);
setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
@@ -350,6 +360,11 @@
setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
+ setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
+ setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
+ setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
+ setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
+ setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
}
computeRegisterProperties();
diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp
index aa261dc..e469422 100644
--- a/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/lib/Target/Sparc/SparcISelLowering.cpp
@@ -586,6 +586,16 @@
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
setOperationAction(ISD::FPOW , MVT::f64, Expand);
setOperationAction(ISD::FPOW , MVT::f32, Expand);
+ setOperationAction(ISD::FLOG , MVT::f64, Expand);
+ setOperationAction(ISD::FLOG , MVT::f32, Expand);
+ setOperationAction(ISD::FLOG2, MVT::f64, Expand);
+ setOperationAction(ISD::FLOG2, MVT::f32, Expand);
+ setOperationAction(ISD::FLOG10, MVT::f64, Expand);
+ setOperationAction(ISD::FLOG10, MVT::f32, Expand);
+ setOperationAction(ISD::FEXP , MVT::f64, Expand);
+ setOperationAction(ISD::FEXP , MVT::f32, Expand);
+ setOperationAction(ISD::FEXP2, MVT::f64, Expand);
+ setOperationAction(ISD::FEXP2, MVT::f32, Expand);
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 2cdd93c..9b492fb 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -494,6 +494,22 @@
setOperationAction(ISD::FPOW , MVT::f64 , Expand);
setOperationAction(ISD::FPOW , MVT::f80 , Expand);
+ setOperationAction(ISD::FLOG, MVT::f32, Expand);
+ setOperationAction(ISD::FLOG, MVT::f64, Expand);
+ setOperationAction(ISD::FLOG, MVT::f80, Expand);
+ setOperationAction(ISD::FLOG2, MVT::f32, Expand);
+ setOperationAction(ISD::FLOG2, MVT::f64, Expand);
+ setOperationAction(ISD::FLOG2, MVT::f80, Expand);
+ setOperationAction(ISD::FLOG10, MVT::f32, Expand);
+ setOperationAction(ISD::FLOG10, MVT::f64, Expand);
+ setOperationAction(ISD::FLOG10, MVT::f80, Expand);
+ setOperationAction(ISD::FEXP, MVT::f32, Expand);
+ setOperationAction(ISD::FEXP, MVT::f64, Expand);
+ setOperationAction(ISD::FEXP, MVT::f80, Expand);
+ setOperationAction(ISD::FEXP2, MVT::f32, Expand);
+ setOperationAction(ISD::FEXP2, MVT::f64, Expand);
+ setOperationAction(ISD::FEXP2, MVT::f80, Expand);
+
// First set operation action for all vector types to expand. Then we
// will selectively turn on ones that can be effectively codegen'd.
for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;