commit 779e640657e14420f8e796b7b179948038fc0707
author Alkis Evlogimenos <alkis@evlogimenos.com> Wed Feb 18 23:15:23 2004 +0000
committer Alkis Evlogimenos <alkis@evlogimenos.com> Wed Feb 18 23:15:23 2004 +0000
tree 48bc3d8bfed1d465296e546c7470772d4cc22a8e
parent 52f8f56ef4efaceee7535d804bf0a844cf530c57

Implement assignment correctness verification.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11609 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/RegAllocLinearScan.cpp

diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index 0140410..6791220 100644
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -206,6 +206,19 @@
                 std::cerr << mri_->getName(reg) << '\n';
             }
         }
+
+        void verifyAssignment() const {
+            for (Virt2PhysMap::const_iterator i = v2pMap_.begin(),
+                     e = v2pMap_.end(); i != e; ++i)
+                for (Virt2PhysMap::const_iterator i2 = i; i2 != e; ++i2)
+                    if (mri_->areAliases(i->second, i2->second)) {
+                        const LiveIntervals::Interval
+                            &in = li_->getInterval(i->second),
+                            &in2 = li_->getInterval(i2->second);
+                        assert(!in.overlaps(in2) &&
+                               "overlapping intervals for same register!");
+                    }
+        }
     };
 }
 
@@ -290,6 +303,8 @@
 
     DEBUG(printVirtRegAssignment());
     DEBUG(std::cerr << "finished register allocation\n");
+    // this is a slow operations do not uncomment
+    // DEBUG(verifyAssignment());
 
     const TargetInstrInfo& tii = tm_->getInstrInfo();