Convert tabs to spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21452 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp
index bc09f1c..49af9b6 100644
--- a/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -1306,7 +1306,7 @@
}
} // switch
return;
- }
+ }
}
unsigned PPCOpcode = getPPCOpcodeForSetCCOpcode(Opcode);
diff --git a/lib/Target/PowerPC/PPC64ISelPattern.cpp b/lib/Target/PowerPC/PPC64ISelPattern.cpp
index e196a2b..e5c2f40 100644
--- a/lib/Target/PowerPC/PPC64ISelPattern.cpp
+++ b/lib/Target/PowerPC/PPC64ISelPattern.cpp
@@ -218,8 +218,9 @@
std::pair<SDOperand, SDOperand>
PPC64TargetLowering::LowerCallTo(SDOperand Chain,
- const Type *RetTy, bool isVarArg,
- SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) {
+ const Type *RetTy, bool isVarArg,
+ SDOperand Callee, ArgListTy &Args,
+ SelectionDAG &DAG) {
// args_to_use will accumulate outgoing args for the ISD::CALL case in
// SelectExpr to use to put the arguments in the appropriate registers.
std::vector<SDOperand> args_to_use;
@@ -1519,7 +1520,7 @@
case 3:
assert(N.getOperand(1).getValueType() == MVT::i32 &&
N.getOperand(2).getValueType() == MVT::i32 &&
- "Unknown two-register value!");
+ "Unknown two-register value!");
Select(N.getOperand(0));
Tmp1 = SelectExpr(N.getOperand(1));
Tmp2 = SelectExpr(N.getOperand(2));
diff --git a/lib/Target/PowerPC/PPC64RegisterInfo.cpp b/lib/Target/PowerPC/PPC64RegisterInfo.cpp
index 46f0e1c..e725da6 100644
--- a/lib/Target/PowerPC/PPC64RegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPC64RegisterInfo.cpp
@@ -50,7 +50,7 @@
static const TargetRegisterClass *getClass(unsigned SrcReg) {
if (PPC64::FPRCRegisterClass->contains(SrcReg))
- return PPC64::FPRCRegisterClass;
+ return PPC64::FPRCRegisterClass;
assert(PPC64::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
return PPC64::GPRCRegisterClass;
}
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 84c05cb..a516a8b 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -263,8 +263,9 @@
std::pair<SDOperand, SDOperand>
PPC32TargetLowering::LowerCallTo(SDOperand Chain,
- const Type *RetTy, bool isVarArg,
- SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) {
+ const Type *RetTy, bool isVarArg,
+ SDOperand Callee, ArgListTy &Args,
+ SelectionDAG &DAG) {
// args_to_use will accumulate outgoing args for the ISD::CALL case in
// SelectExpr to use to put the arguments in the appropriate registers.
std::vector<SDOperand> args_to_use;
@@ -2366,7 +2367,7 @@
case 3:
assert(N.getOperand(1).getValueType() == MVT::i32 &&
N.getOperand(2).getValueType() == MVT::i32 &&
- "Unknown two-register value!");
+ "Unknown two-register value!");
Select(N.getOperand(0));
Tmp1 = SelectExpr(N.getOperand(1));
Tmp2 = SelectExpr(N.getOperand(2));
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 66bbea7..bbcf7c3 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -50,7 +50,7 @@
static const TargetRegisterClass *getClass(unsigned SrcReg) {
if (PPC32::FPRCRegisterClass->contains(SrcReg))
- return PPC32::FPRCRegisterClass;
+ return PPC32::FPRCRegisterClass;
assert(PPC32::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
return PPC32::GPRCRegisterClass;
}