commit 78703ddafe3d037f75d8ca188e4829d238289ac3
author Evan Cheng <evan.cheng@apple.com> Mon Jul 27 18:44:00 2009 +0000
committer Evan Cheng <evan.cheng@apple.com> Mon Jul 27 18:44:00 2009 +0000
tree 70c9854e52d229b6a557d537dafc36ec8c0a8982
parent ad895a8dec0c52f38148b19e84d9e67a9e2b25dd

convertToThreeAddress can't handle Thumb2 instructions (which don't have same address mode as ARM instructions).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77230 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMBaseInstrInfo.cpp

diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 5703f6b..6e1f558 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -39,6 +39,8 @@
 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
                                         MachineBasicBlock::iterator &MBBI,
                                         LiveVariables *LV) const {
+  // FIXME: Thumb2 support.
+
   if (!EnableARM3Addr)
     return NULL;
 
@@ -88,22 +90,19 @@
         // add more than 1 instruction. Abandon!
         return NULL;
       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
-                         get(isSub ? getOpcode(ARMII::SUBri) :
-                             getOpcode(ARMII::ADDri)), WBReg)
+                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
         .addReg(BaseReg).addImm(Amt)
         .addImm(Pred).addReg(0).addReg(0);
     } else if (Amt != 0) {
       ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
       unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
-                         get(isSub ? getOpcode(ARMII::SUBrs) :
-                             getOpcode(ARMII::ADDrs)), WBReg)
+                         get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
         .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
         .addImm(Pred).addReg(0).addReg(0);
     } else
       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
-                         get(isSub ? getOpcode(ARMII::SUBrr) :
-                             getOpcode(ARMII::ADDrr)), WBReg)
+                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
         .addReg(BaseReg).addReg(OffReg)
         .addImm(Pred).addReg(0).addReg(0);
     break;
@@ -114,14 +113,12 @@
     if (OffReg == 0)
       // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
-                         get(isSub ? getOpcode(ARMII::SUBri) : 
-                             getOpcode(ARMII::ADDri)), WBReg)
+                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
         .addReg(BaseReg).addImm(Amt)
         .addImm(Pred).addReg(0).addReg(0);
     else
       UpdateMI = BuildMI(MF, MI->getDebugLoc(),
-                         get(isSub ? getOpcode(ARMII::SUBrr) :
-                             getOpcode(ARMII::ADDrr)), WBReg)
+                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
         .addReg(BaseReg).addReg(OffReg)
         .addImm(Pred).addReg(0).addReg(0);
     break;