Clean up some confusing language, and use more realistic examples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178828 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index fb311d8..0ba75e5 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -364,11 +364,10 @@
/// condition code in Cond.
///
/// When successful, also return the latency in cycles from TrueReg,
- /// FalseReg, and Cond to the destination register. The Cond latency should
- /// compensate for a conditional branch being removed. For example, if a
- /// conditional branch has a 3 cycle latency from the condition code read,
- /// and a cmov instruction has a 2 cycle latency from the condition code
- /// read, CondCycles should be returned as -1.
+ /// FalseReg, and Cond to the destination register. In most cases, a select
+ /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
+ ///
+ /// Some x86 implementations have 2-cycle cmov instructions.
///
/// @param MBB Block where select instruction would be inserted.
/// @param Cond Condition returned by AnalyzeBranch.