Modify the TargetLowering::getPackedTypeBreakdown method to also return the
unpromoted element type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27273 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index b9c10ce..922245f 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -148,11 +148,13 @@
///
/// This method returns the number and type of the resultant breakdown.
///
-MVT::ValueType TargetLowering::getPackedTypeBreakdown(const PackedType *PTy,
- unsigned &NumVals) const {
+unsigned TargetLowering::getPackedTypeBreakdown(const PackedType *PTy,
+ MVT::ValueType &PTyElementVT,
+ MVT::ValueType &PTyLegalElementVT) const {
// Figure out the right, legal destination reg to copy into.
unsigned NumElts = PTy->getNumElements();
MVT::ValueType EltTy = getValueType(PTy->getElementType());
+ PTyElementVT = EltTy;
unsigned NumVectorRegs = 1;
@@ -170,13 +172,14 @@
VT = getVectorType(EltTy, NumElts);
MVT::ValueType DestVT = getTypeToTransformTo(VT);
+ PTyLegalElementVT = DestVT;
if (DestVT < VT) {
// Value is expanded, e.g. i64 -> i16.
- NumVals = NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT));
+ return NumVectorRegs*(MVT::getSizeInBits(VT)/MVT::getSizeInBits(DestVT));
} else {
// Otherwise, promotion or legal types use the same number of registers as
// the vector decimated to the appropriate level.
- NumVals = NumVectorRegs;
+ return NumVectorRegs;
}
return DestVT;