Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
pseudonym.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116512 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index fa27a75..b5f534f 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -645,7 +645,7 @@
// Encode the shift operation.
switch (Opcode) {
default: break;
- case ARM::MOVrx:
+ case ARM::RRX:
// rrx
Binary |= 0x6 << 4;
break;
@@ -748,7 +748,7 @@
// Materialize jumptable address.
emitLEApcrelJTInstruction(MI);
break;
- case ARM::MOVrx:
+ case ARM::RRX:
case ARM::MOVsrl_flag:
case ARM::MOVsra_flag:
emitPseudoMoveInstruction(MI);
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 8fc5c3c..5a2070d 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1686,9 +1686,9 @@
Requires<[IsARM, HasV6T2]>;
let Uses = [CPSR] in
-def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
- "mov", "\t$dst, $src, rrx",
- [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
+def RRX: AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), Pseudo, IIC_iMOVsi,
+ "rrx", "\t$Rd, $Rm",
+ [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP;
// These aren't really mov instructions, but we have to define them this way
// due to flag operands.
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 25b9428..5c5ef18 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -1598,7 +1598,7 @@
defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
let Uses = [CPSR] in {
-def t2MOVrx : T2sI<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
+def t2RRX : T2sI<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi,
"rrx", "\t$dst, $src",
[(set rGPR:$dst, (ARMrrx rGPR:$src))]> {
let Inst{31-27} = 0b11101;