Update tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138116 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 9163629..8da7be0 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -1114,6 +1114,10 @@
"rsb", "\t$Rd, $Rn, #0",
[(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
+def : InstAlias<"neg${s}${p} $Rd, $Rm",
+ (tRSB tGPR:$Rd, CPSR, tGPR:$Rm, pred:$p)>,
+ Requires<[IsThumb]>;
+
// Subtract with carry register
let Uses = [CPSR] in
def tSBC : // A8.6.151
diff --git a/test/CodeGen/ARM/avoid-cpsr-rmw.ll b/test/CodeGen/ARM/avoid-cpsr-rmw.ll
index d0c4f3a..d148bbe 100644
--- a/test/CodeGen/ARM/avoid-cpsr-rmw.ll
+++ b/test/CodeGen/ARM/avoid-cpsr-rmw.ll
@@ -6,9 +6,9 @@
define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
entry:
; CHECK: t:
-; CHECK: muls r2, r3, r2
+; CHECK: muls r2, r2, r3
; CHECK-NEXT: mul r0, r0, r1
-; CHECK-NEXT: muls r0, r2, r0
+; CHECK-NEXT: muls r0, r0, r2
%0 = mul nsw i32 %a, %b
%1 = mul nsw i32 %c, %d
%2 = mul nsw i32 %0, %1
diff --git a/test/CodeGen/Thumb2/thumb2-mls.ll b/test/CodeGen/Thumb2/thumb2-mls.ll
index fc9e6ba..24c45c5 100644
--- a/test/CodeGen/Thumb2/thumb2-mls.ll
+++ b/test/CodeGen/Thumb2/thumb2-mls.ll
@@ -15,5 +15,5 @@
ret i32 %tmp2
}
; CHECK: f2:
-; CHECK: muls r0, r1
+; CHECK: muls r0, r0, r1
diff --git a/test/CodeGen/Thumb2/thumb2-mul.ll b/test/CodeGen/Thumb2/thumb2-mul.ll
index 8d1de55b..bb97d97 100644
--- a/test/CodeGen/Thumb2/thumb2-mul.ll
+++ b/test/CodeGen/Thumb2/thumb2-mul.ll
@@ -2,7 +2,7 @@
define i32 @f1(i32 %a, i32 %b, i32 %c) {
; CHECK: f1:
-; CHECK: muls r0, r1
+; CHECK: muls r0, r0, r1
%tmp = mul i32 %a, %b
ret i32 %tmp
}