Add normal and trunc stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70724 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/MSP430/MSP430ISelLowering.cpp b/lib/Target/MSP430/MSP430ISelLowering.cpp
index bd0db9b..81494fc 100644
--- a/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -39,6 +39,7 @@
TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
// Set up the register classes.
+ addRegisterClass(MVT::i8, MSP430::GR8RegisterClass);
addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
// Compute derived properties from the register classes
@@ -59,6 +60,9 @@
setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
+ // We don't have any truncstores
+ setTruncStoreAction(MVT::i16, MVT::i8, Expand);
+
setOperationAction(ISD::SRA, MVT::i16, Custom);
setOperationAction(ISD::RET, MVT::Other, Custom);
}
diff --git a/lib/Target/MSP430/MSP430InstrInfo.td b/lib/Target/MSP430/MSP430InstrInfo.td
index 4a261e4..2554135 100644
--- a/lib/Target/MSP430/MSP430InstrInfo.td
+++ b/lib/Target/MSP430/MSP430InstrInfo.td
@@ -35,12 +35,17 @@
// MSP430 Operand Definitions.
//===----------------------------------------------------------------------===//
-// Address operand
+// Address operands
def memsrc : Operand<i16> {
let PrintMethod = "printSrcMemOperand";
let MIOperandInfo = (ops i16imm, GR16);
}
+def memdst : Operand<i16> {
+ let PrintMethod = "printSrcMemOperand";
+ let MIOperandInfo = (ops i16imm, GR16);
+}
+
//===----------------------------------------------------------------------===//
// MSP430 Complex Pattern Definitions.
@@ -106,6 +111,20 @@
"mov.b\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
+def MOV8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
+ "mov.b\t{$src, $dst|$dst, $src}",
+ [(store (i8 imm:$src), addr:$dst)]>;
+def MOV16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
+ "mov.w\t{$src, $dst|$dst, $src}",
+ [(store (i16 imm:$src), addr:$dst)]>;
+
+def MOV8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
+ "mov.b\t{$src, $dst|$dst, $src}",
+ [(store GR8:$src, addr:$dst)]>;
+def MOV16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
+ "mov.w\t{$src, $dst|$dst, $src}",
+ [(store GR16:$src, addr:$dst)]>;
+
//===----------------------------------------------------------------------===//
// Arithmetic Instructions
@@ -273,3 +292,7 @@
// extload
def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
+
+// truncs
+def : Pat<(i8 (trunc GR16:$src)),
+ (EXTRACT_SUBREG GR16:$src, subreg_8bit)>;
diff --git a/lib/Target/MSP430/MSP430RegisterInfo.td b/lib/Target/MSP430/MSP430RegisterInfo.td
index 7564402..4078626 100644
--- a/lib/Target/MSP430/MSP430RegisterInfo.td
+++ b/lib/Target/MSP430/MSP430RegisterInfo.td
@@ -65,6 +65,8 @@
[PCB, SPB, SRB, CGB, FPB,
R5B, R6B, R7B, R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
+def subreg_8bit : PatLeaf<(i32 1)>;
+
def GR8 : RegisterClass<"MSP430", [i8], 8,
// Volatile registers
[R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B,