commit 7b441dc966804e363a76db00cb238af6d93d8409
author Andrew Lenharth <andrewl@lenharth.org> Thu Nov 10 16:59:55 2005 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Thu Nov 10 16:59:55 2005 +0000
tree d7f75b740dad141073d2311ec0e576480c01a326
parent 105b2f5374d970822d6f33f7ec5d2ed1e9ef9c29

fix a bunch of regressions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24269 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaISelPattern.cpp

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 96684ba..eb13486 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1295,11 +1295,11 @@
       if (SrcType == MVT::f32)
         {
           Tmp2 = MakeReg(MVT::f64);
-          BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Alpha::F31).addReg(Tmp1);
+          BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Tmp1);
           Tmp1 = Tmp2;
         }
       Tmp2 = MakeReg(MVT::f64);
-      BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Alpha::F31).addReg(Tmp1);
+      BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Tmp1);
       MoveFP2Int(Tmp2, Result, true);
 
       return Result;