commit 7b5f7ed5c3714b7584460b40d96825d27f983385
author Scott Michel <scottm@aero.org> Sat Dec 15 00:38:50 2007 +0000
committer Scott Michel <scottm@aero.org> Sat Dec 15 00:38:50 2007 +0000
tree 7a62987b26d5e86ee5abd5d82cd78cb45cd02d34
parent e49cb571be5900f944adb54624ca04a00de1c396

Start committing working test cases for CellSPU.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45050 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/CellSPU/SPUInstrInfo.td

diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td
index faa6a7c..2ec14d2 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.td
+++ b/lib/Target/CellSPU/SPUInstrInfo.td
@@ -1127,7 +1127,7 @@
 def ANDHIr16:
     RI10Form<0b10101000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
       "andhi\t$rT, $rA, $val", IntegerOp,
-      [(set R16C:$rT, (and R16C:$rA, i16ImmSExt10:$val))]>;
+      [(set R16C:$rT, (and R16C:$rA, i16ImmU10:$val))]>;
 
 def ANDIv4i32:
     RI10Form<0b00101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),