When doing the very-late shift-and address-mode optimization,
create a new DAG node to represent the new shift to keep the
DAG consistent, even though it'll almost always be folded into
the address.
If a user of the resulting address has multiple uses, the
nodes may get revisited by a later MatchAddress call, in which
case DAG inconsistencies do matter.
This fixes PR2849.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57465 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 50c8f5b..b013415 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -989,8 +989,11 @@
SDValue(C2, 0), SDValue(C1, 0));
SDValue NewAND = CurDAG->getNode(ISD::AND, N.getValueType(),
Shift.getOperand(0), NewANDMask);
+ SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, N.getValueType(),
+ NewAND, SDValue(C1, 0));
NewANDMask.getNode()->setNodeId(Shift.getNode()->getNodeId());
NewAND.getNode()->setNodeId(N.getNode()->getNodeId());
+ CurDAG->ReplaceAllUsesWith(N, NewSHIFT);
AM.Scale = 1 << ShiftCst;
AM.IndexReg = NewAND;
diff --git a/test/CodeGen/X86/pr2849.ll b/test/CodeGen/X86/pr2849.ll
new file mode 100644
index 0000000..673598f
--- /dev/null
+++ b/test/CodeGen/X86/pr2849.ll
@@ -0,0 +1,38 @@
+; RUN: llvm-as < %s | llc
+; PR2849
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+ %struct.BaseBoundPtrs = type { i8*, i8* }
+ %struct.HashEntry = type { %struct.BaseBoundPtrs }
+ %struct.NODE = type { i8, i8, %struct.anon }
+ %struct.anon = type { %struct.xlist }
+ %struct.xlist = type { %struct.NODE*, %struct.NODE* }
+ %struct.xvect = type { %struct.NODE** }
+@hash_table_begin = external global %struct.HashEntry*
+
+define void @obshow() {
+entry:
+ %tmp = load %struct.HashEntry** @hash_table_begin, align 8
+ br i1 false, label %xlygetvalue.exit, label %xlygetvalue.exit
+
+xlygetvalue.exit:
+ %storemerge.in.i = phi %struct.NODE** [ null, %entry ], [ null, %entry ]
+ %storemerge.i = load %struct.NODE** %storemerge.in.i
+ %tmp1 = ptrtoint %struct.NODE** %storemerge.in.i to i64
+ %tmp2 = lshr i64 %tmp1, 3
+ %tmp3 = and i64 %tmp2, 2147483647
+ %tmp4 = getelementptr %struct.HashEntry* %tmp, i64 %tmp3, i32 0, i32 1
+ %tmp7 = load i8** %tmp4, align 8
+ %tmp8 = getelementptr %struct.NODE* %storemerge.i, i64 0, i32 2
+ %tmp9 = bitcast %struct.anon* %tmp8 to %struct.NODE***
+ %tmp11 = load %struct.NODE*** %tmp9, align 8
+ %tmp12 = ptrtoint %struct.NODE** %tmp11 to i64
+ %tmp13 = lshr i64 %tmp12, 3
+ %tmp14 = and i64 %tmp13, 2147483647
+ %tmp15 = getelementptr %struct.HashEntry* %tmp, i64 %tmp14, i32 0, i32 1
+ call fastcc void @xlprint(i8** %tmp4, i8* %tmp7, i8** %tmp15)
+ ret void
+}
+
+declare fastcc void @xlprint(i8**, i8*, i8**)