Fix an oversight that may be causing PR617.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22753 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index c2d5de8..549b480 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -626,12 +626,21 @@
if (N2.getOpcode() == ISD::ADD || N2.getOpcode() == ISD::SUB ||
N2.getOpcode() == ISD::XOR) {
// Simplify X == (X+Z) --> Z == 0
- if (N2.getOperand(0) == N1)
+ if (N2.getOperand(0) == N1) {
return getSetCC(VT, N2.getOperand(1),
getConstant(0, N2.getValueType()), Cond);
- else if (N2.getOperand(1) == N1)
- return getSetCC(VT, N2.getOperand(0), getConstant(0, N2.getValueType()),
- Cond);
+ } else if (N2.getOperand(1) == N1) {
+ if (isCommutativeBinOp(N2.getOpcode())) {
+ return getSetCC(VT, N2.getOperand(0),
+ getConstant(0, N2.getValueType()), Cond);
+ } else {
+ assert(N2.getOpcode() == ISD::SUB && "Unexpected operation!");
+ // X == (Z-X) --> X<<1 == Z
+ return getSetCC(VT, getNode(ISD::SHL, N2.getValueType(), N1,
+ getConstant(1, TLI.getShiftAmountTy())),
+ N2.getOperand(0), Cond);
+ }
+ }
}
}