When scheduling a block in parts, keep track of the overall
instruction index across each part. Instruction indices are used
to make live range queries, and live ranges can extend beyond
scheduling region boundaries.
Refactor the ScheduleDAGSDNodes class some more so that it
doesn't have to worry about this additional information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64288 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
index 1cd893e..0c343f9 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -629,6 +629,7 @@
// Public Constructor Functions
//===----------------------------------------------------------------------===//
-llvm::ScheduleDAG* llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) {
+llvm::ScheduleDAGSDNodes *
+llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) {
return new ScheduleDAGFast(*IS->MF);
}
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
index c78ecb8..e63484e 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
@@ -260,8 +260,8 @@
/// createTDListDAGScheduler - This creates a top-down list scheduler with a
/// new hazard recognizer. This scheduler takes ownership of the hazard
/// recognizer and deletes it when done.
-ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAGISel *IS,
- bool Fast) {
+ScheduleDAGSDNodes *
+llvm::createTDListDAGScheduler(SelectionDAGISel *IS, bool Fast) {
return new ScheduleDAGList(*IS->MF,
new LatencyPriorityQueue(),
IS->CreateTargetHazardRecognizer());
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 94006b5..07274b2 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1358,8 +1358,8 @@
// Public Constructor Functions
//===----------------------------------------------------------------------===//
-llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
- bool) {
+llvm::ScheduleDAGSDNodes *
+llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) {
const TargetMachine &TM = IS->TM;
const TargetInstrInfo *TII = TM.getInstrInfo();
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
@@ -1372,8 +1372,8 @@
return SD;
}
-llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
- bool) {
+llvm::ScheduleDAGSDNodes *
+llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, bool) {
const TargetMachine &TM = IS->TM;
const TargetInstrInfo *TII = TM.getInstrInfo();
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index 2620c72..ea9f47b 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -26,6 +26,14 @@
: ScheduleDAG(mf) {
}
+/// Run - perform scheduling.
+///
+void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb,
+ MachineBasicBlock::iterator insertPos) {
+ DAG = dag;
+ ScheduleDAG::Run(bb, insertPos);
+}
+
SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
SUnit *SU = NewSUnit(Old->getNode());
SU->OrigNode = Old->OrigNode;
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
index f340d38..af3adaa 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
@@ -35,10 +35,17 @@
///
class ScheduleDAGSDNodes : public ScheduleDAG {
public:
+ SelectionDAG *DAG; // DAG of the current basic block
+
explicit ScheduleDAGSDNodes(MachineFunction &mf);
virtual ~ScheduleDAGSDNodes() {}
+ /// Run - perform scheduling.
+ ///
+ void Run(SelectionDAG *dag, MachineBasicBlock *bb,
+ MachineBasicBlock::iterator insertPos);
+
/// isPassiveNode - Return true if the node is a non-scheduled leaf.
///
static bool isPassiveNode(SDNode *Node) {
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
index 1d369c1..852c430 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
@@ -125,7 +125,8 @@
} else {
// Create the reg, emit the copy.
VRBase = MRI.createVirtualRegister(DstRC);
- bool Emitted = TII->copyRegToReg(*BB, End, VRBase, SrcReg, DstRC, SrcRC);
+ bool Emitted = TII->copyRegToReg(*BB, InsertPos, VRBase, SrcReg,
+ DstRC, SrcRC);
if (!Emitted) {
cerr << "Unable to issue a copy instruction!\n";
abort();
@@ -381,7 +382,7 @@
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
MI->addOperand(MachineOperand::CreateImm(SubIdx));
- BB->insert(End, MI);
+ BB->insert(InsertPos, MI);
} else if (Opc == TargetInstrInfo::INSERT_SUBREG ||
Opc == TargetInstrInfo::SUBREG_TO_REG) {
SDValue N0 = Node->getOperand(0);
@@ -414,7 +415,7 @@
// Add the subregster being inserted
AddOperand(MI, N1, 0, 0, VRBaseMap);
MI->addOperand(MachineOperand::CreateImm(SubIdx));
- BB->insert(End, MI);
+ BB->insert(InsertPos, MI);
} else
assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg");
@@ -478,9 +479,9 @@
// Insert this instruction into the basic block using a target
// specific inserter which may returns a new basic block.
BB = TLI->EmitInstrWithCustomInserter(MI, BB);
- Begin = End = BB->end();
+ InsertPos = BB->end();
} else {
- BB->insert(End, MI);
+ BB->insert(InsertPos, MI);
}
// Additional results must be an physical register def.
@@ -530,7 +531,8 @@
else
DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
Node->getOperand(1).getValueType());
- bool Emitted = TII->copyRegToReg(*BB, End, DestReg, SrcReg, DstTRC, SrcTRC);
+ bool Emitted = TII->copyRegToReg(*BB, InsertPos, DestReg, SrcReg,
+ DstTRC, SrcTRC);
if (!Emitted) {
cerr << "Unable to issue a copy instruction!\n";
abort();
@@ -590,7 +592,7 @@
break;
}
}
- BB->insert(End, MI);
+ BB->insert(InsertPos, MI);
break;
}
}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index f8d79ce..ed6e4fb 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -137,8 +137,8 @@
//===--------------------------------------------------------------------===//
/// createDefaultScheduler - This creates an instruction scheduler appropriate
/// for the target.
- ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
- bool Fast) {
+ ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
+ bool Fast) {
const TargetLowering &TLI = IS->getTargetLowering();
if (Fast)
@@ -662,12 +662,12 @@
if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
// Schedule machine code.
- ScheduleDAG *Scheduler = CreateScheduler();
+ ScheduleDAGSDNodes *Scheduler = CreateScheduler();
if (TimePassesIsEnabled) {
NamedRegionTimer T("Instruction Scheduling", GroupName);
- Scheduler->Run(CurDAG, BB, BB->end(), BB->end());
+ Scheduler->Run(CurDAG, BB, BB->end());
} else {
- Scheduler->Run(CurDAG, BB, BB->end(), BB->end());
+ Scheduler->Run(CurDAG, BB, BB->end());
}
if (ViewSUnitDAGs) Scheduler->viewGraph();
@@ -1068,7 +1068,7 @@
/// via the SchedulerRegistry, use it, otherwise select the
/// one preferred by the target.
///
-ScheduleDAG *SelectionDAGISel::CreateScheduler() {
+ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
if (!Ctor) {