Implement BR_CC and BRTWOWAY_CC. This allows the removal of a rather nasty
fixme from the PowerPC backend. Emit slightly better code for legalizing
select_cc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22805 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index e898916..c0ae2ac 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -90,6 +90,7 @@
addRegisterClass(MVT::f32, Alpha::FPRCRegisterClass);
setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
+ setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index 5428a8b..f4231a3 100644
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -57,6 +57,7 @@
addRegisterClass(MVT::i1, IA64::PRRegisterClass);
setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
+ setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
setSetCCResultType(MVT::i1);
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index d06542d..cd2fc16 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -66,6 +66,10 @@
setOperationAction(ISD::SELECT, MVT::i32, Expand);
setOperationAction(ISD::SELECT, MVT::f32, Expand);
setOperationAction(ISD::SELECT, MVT::f64, Expand);
+
+ // PowerPC does not have BRCOND* which requires SetCC
+ setOperationAction(ISD::BRCOND, MVT::Other, Expand);
+ setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
// PowerPC does not have FP_TO_UINT
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 75f568f..4e674dc 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -713,22 +713,11 @@
void ISel::SelectBranchCC(SDOperand N)
{
MachineBasicBlock *Dest =
- cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
+ cast<BasicBlockSDNode>(N.getOperand(4))->getBasicBlock();
Select(N.getOperand(0)); //chain
-
- // FIXME: Until we have Branch_CC and Branch_Twoway_CC, we're going to have to
- // Fake it up by hand by checking to see if op 1 is a SetCC, or a boolean.
- unsigned CCReg;
- ISD::CondCode CC;
- SDOperand Cond = N.getOperand(1);
- if (Cond.getOpcode() == ISD::SETCC) {
- CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
- CCReg = SelectCC(Cond.getOperand(0), Cond.getOperand(1), CC);
- } else {
- CC = ISD::SETNE;
- CCReg = SelectCC(Cond, ISelDAG->getConstant(0, Cond.getValueType()), CC);
- }
+ ISD::CondCode CC = cast<CondCodeSDNode>(N.getOperand(1))->get();
+ unsigned CCReg = SelectCC(N.getOperand(2), N.getOperand(3), CC);
unsigned Opc = getBCCForSetCC(CC);
// Iterate to the next basic block
@@ -739,9 +728,9 @@
// and build a PowerPC branch pseudo-op, suitable for long branch conversion
// if necessary by the branch selection pass. Otherwise, emit a standard
// conditional branch.
- if (N.getOpcode() == ISD::BRCONDTWOWAY) {
+ if (N.getOpcode() == ISD::BRTWOWAY_CC) {
MachineBasicBlock *Fallthrough =
- cast<BasicBlockSDNode>(N.getOperand(3))->getBasicBlock();
+ cast<BasicBlockSDNode>(N.getOperand(5))->getBasicBlock();
if (Dest != It) {
BuildMI(BB, PPC::COND_BRANCH, 4).addReg(CCReg).addImm(Opc)
.addMBB(Dest).addMBB(Fallthrough);
@@ -1882,8 +1871,8 @@
BuildMI(BB, PPC::B, 1).addMBB(Dest);
return;
}
- case ISD::BRCOND:
- case ISD::BRCONDTWOWAY:
+ case ISD::BR_CC:
+ case ISD::BRTWOWAY_CC:
SelectBranchCC(N);
return;
case ISD::CopyToReg:
diff --git a/lib/Target/Sparc/SparcV8ISelPattern.cpp b/lib/Target/Sparc/SparcV8ISelPattern.cpp
index 346f058..754c16b 100644
--- a/lib/Target/Sparc/SparcV8ISelPattern.cpp
+++ b/lib/Target/Sparc/SparcV8ISelPattern.cpp
@@ -55,6 +55,7 @@
addRegisterClass(MVT::f32, V8::FPRCRegisterClass);
setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
+ setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
setOperationAction(ISD::EXTLOAD, MVT::f32, Promote);
diff --git a/lib/Target/SparcV8/SparcV8ISelPattern.cpp b/lib/Target/SparcV8/SparcV8ISelPattern.cpp
index 346f058..754c16b 100644
--- a/lib/Target/SparcV8/SparcV8ISelPattern.cpp
+++ b/lib/Target/SparcV8/SparcV8ISelPattern.cpp
@@ -55,6 +55,7 @@
addRegisterClass(MVT::f32, V8::FPRCRegisterClass);
setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
+ setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
setOperationAction(ISD::EXTLOAD, MVT::f32, Promote);
diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index db95e91..6ff8c72 100644
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -152,6 +152,7 @@
setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
+ setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);