commit 7ce45783531cfa81bfd7be561ea7e4738e8c6ca8
author Evan Cheng <evan.cheng@apple.com> Mon Nov 13 23:36:35 2006 +0000
committer Evan Cheng <evan.cheng@apple.com> Mon Nov 13 23:36:35 2006 +0000
tree 459ce71956b931173c43b156295d14e18f4748fc
parent d7de496b23fca8145f777a56281457bf64e8bbad

Matches MachineInstr changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31712 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Sparc/SparcInstrInfo.cpp

diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp
index 0a982ff..23f2e42 100644
--- a/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -19,7 +19,7 @@
 
 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
   : TargetInstrInfo(SparcInsts, sizeof(SparcInsts)/sizeof(SparcInsts[0])),
-    RI(ST) {
+    RI(ST, *this) {
 }
 
 static bool isZeroImm(const MachineOperand &op) {

lib/Target/Sparc/SparcRegisterInfo.cpp

diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index 81ebdba..bd2da73 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -23,9 +23,10 @@
 #include <iostream>
 using namespace llvm;
 
-SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st)
+SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
+                                     const TargetInstrInfo &tii)
   : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
-    Subtarget(st) {
+    Subtarget(st), TII(tii) {
 }
 
 void SparcRegisterInfo::
@@ -81,10 +82,10 @@
     if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
         MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
       if (OpNum == 0)    // COPY -> STORE
-        return BuildMI(SP::STri, 3).addFrameIndex(FI).addImm(0)
+        return BuildMI(TII, SP::STri, 3).addFrameIndex(FI).addImm(0)
                                    .addReg(MI->getOperand(2).getReg());
       else               // COPY -> LOAD
-        return BuildMI(SP::LDri, 2, MI->getOperand(0).getReg())
+        return BuildMI(TII, SP::LDri, 2, MI->getOperand(0).getReg())
                       .addFrameIndex(FI).addImm(0);
     }
     break;
@@ -93,10 +94,10 @@
     // FALLTHROUGH
   case SP::FMOVD:
     if (OpNum == 0)  // COPY -> STORE
-      return BuildMI(isFloat ? SP::STFri : SP::STDFri, 3)
+      return BuildMI(TII, isFloat ? SP::STFri : SP::STDFri, 3)
                .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
     else             // COPY -> LOAD
-      return BuildMI(isFloat ? SP::LDFri : SP::LDDFri, 2, 
+      return BuildMI(TII, isFloat ? SP::LDFri : SP::LDDFri, 2, 
                      MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
     break;
   }

lib/Target/Sparc/SparcRegisterInfo.h

diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h
index bbb11f8..d83060b 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.h
+++ b/lib/Target/Sparc/SparcRegisterInfo.h
@@ -24,8 +24,9 @@
 
 struct SparcRegisterInfo : public SparcGenRegisterInfo {
   SparcSubtarget &Subtarget;
+  const TargetInstrInfo &TII;
   
-  SparcRegisterInfo(SparcSubtarget &st);
+  SparcRegisterInfo(SparcSubtarget &st, const TargetInstrInfo &tii);
 
   /// Code Generation virtual methods...
   void storeRegToStackSlot(MachineBasicBlock &MBB,