Make LowerCallTo and LowerArguments take a DebugLoc
argument. Adjust all callers and overloaded versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63444 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 79ae745..9067c2d 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -740,10 +740,12 @@
Entry.Node = Argument;
Entry.Ty = (const Type *) Type::Int32Ty;
Args.push_back(Entry);
+ // FIXME: is there useful debug info available here?
std::pair<SDValue, SDValue> CallResult =
LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false,
CallingConv::C, false,
- DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG);
+ DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG,
+ DebugLoc::getUnknownLoc());
return CallResult.first;
}
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 1c090ff..753906e 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -356,7 +356,8 @@
bool RetSExt, bool RetZExt, bool isVarArg,
bool isInreg, unsigned CallingConv,
bool isTailCall, SDValue Callee,
- ArgListTy &Args, SelectionDAG &DAG) {
+ ArgListTy &Args, SelectionDAG &DAG,
+ DebugLoc dl) {
int NumBytes = 0;
if (Args.size() > 6)
NumBytes = (Args.size() - 6) * 8;
@@ -374,11 +375,13 @@
// Promote the integer to 64 bits. If the input type is signed use a
// sign extend, otherwise use a zero extend.
if (Args[i].isSExt)
- Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].Node);
+ Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, dl,
+ MVT::i64, Args[i].Node);
else if (Args[i].isZExt)
- Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].Node);
+ Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, dl,
+ MVT::i64, Args[i].Node);
else
- Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, MVT::i64, Args[i].Node);
+ Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, Args[i].Node);
break;
case MVT::i64:
case MVT::f64:
@@ -402,7 +405,8 @@
Ops.push_back(Chain);
Ops.push_back(Callee);
Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
- SDValue TheCall = DAG.getNode(AlphaISD::CALL, RetVals, &Ops[0], Ops.size());
+ SDValue TheCall = DAG.getNode(AlphaISD::CALL, dl,
+ RetVals, &Ops[0], Ops.size());
Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
DAG.getIntPtrConstant(0, true), SDValue());
@@ -416,10 +420,10 @@
AssertKind = ISD::AssertZext;
if (AssertKind != ISD::DELETED_NODE)
- RetVal = DAG.getNode(AssertKind, MVT::i64, RetVal,
+ RetVal = DAG.getNode(AssertKind, dl, MVT::i64, RetVal,
DAG.getValueType(RetTyVT));
- RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
+ RetVal = DAG.getNode(ISD::TRUNCATE, dl, RetTyVT, RetVal);
}
return std::make_pair(RetVal, Chain);
diff --git a/lib/Target/Alpha/AlphaISelLowering.h b/lib/Target/Alpha/AlphaISelLowering.h
index cebd3ac..f165a7f 100644
--- a/lib/Target/Alpha/AlphaISelLowering.h
+++ b/lib/Target/Alpha/AlphaISelLowering.h
@@ -87,7 +87,8 @@
virtual std::pair<SDValue, SDValue>
LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
bool isVarArg, bool isInreg, unsigned CC, bool isTailCall,
- SDValue Callee, ArgListTy &Args, SelectionDAG &DAG);
+ SDValue Callee, ArgListTy &Args, SelectionDAG &DAG,
+ DebugLoc dl);
ConstraintType getConstraintType(const std::string &Constraint) const;
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 86b233c..0718330 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -113,7 +113,8 @@
const Type *RetTy = Op.getNode()->getValueType(0).getTypeForMVT();
std::pair<SDValue, SDValue> CallInfo =
TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
- CallingConv::C, false, Callee, Args, DAG);
+ CallingConv::C, false, Callee, Args, DAG,
+ Op.getNode()->getDebugLoc());
return CallInfo.first;
}
diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index c40f89d..ff7ad90 100644
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -145,7 +145,8 @@
}
void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
- SmallVectorImpl<SDValue> &ArgValues) {
+ SmallVectorImpl<SDValue> &ArgValues,
+ DebugLoc dl) {
//
// add beautiful description of IA64 stack frame format
// here (from intel 24535803.pdf most likely)
@@ -199,7 +200,7 @@
argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
MVT::f64);
if (I->getType() == Type::FloatTy)
- argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt,
+ argt = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, argt,
DAG.getIntPtrConstant(0));
break;
case MVT::i1: // NOTE: as far as C abi stuff goes,
@@ -218,7 +219,7 @@
argt = newroot =
DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64);
if ( getValueType(I->getType()) != MVT::i64)
- argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
+ argt = DAG.getNode(ISD::TRUNCATE, dl, getValueType(I->getType()),
newroot);
break;
}
@@ -230,7 +231,7 @@
// Create the SelectionDAG nodes corresponding to a load
//from this parameter
SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
- argt = newroot = DAG.getLoad(getValueType(I->getType()),
+ argt = newroot = DAG.getLoad(getValueType(I->getType()), dl,
DAG.getEntryNode(), FIN, NULL, 0);
}
++count;
@@ -307,7 +308,8 @@
bool RetSExt, bool RetZExt, bool isVarArg,
bool isInreg, unsigned CallingConv,
bool isTailCall, SDValue Callee,
- ArgListTy &Args, SelectionDAG &DAG) {
+ ArgListTy &Args, SelectionDAG &DAG,
+ DebugLoc dl) {
MachineFunction &MF = DAG.getMachineFunction();
@@ -360,7 +362,7 @@
ExtendKind = ISD::SIGN_EXTEND;
else if (Args[i].isZExt)
ExtendKind = ISD::ZERO_EXTEND;
- Val = DAG.getNode(ExtendKind, MVT::i64, Val);
+ Val = DAG.getNode(ExtendKind, dl, MVT::i64, Val);
// XXX: fall through
}
case MVT::i64:
@@ -373,7 +375,7 @@
break;
case MVT::f32:
//promote to 64-bits
- Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
+ Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
// XXX: fall through
case MVT::f64:
if(RegValuesToPass.size() >= 8) {
@@ -392,19 +394,21 @@
StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
}
SDValue PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
- PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff);
- Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
+ PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, PtrOff);
+ Stores.push_back(DAG.getStore(Chain, dl, ValToStore, PtrOff, NULL, 0));
ArgOffset += ObjSize;
}
if(ValToConvert.getNode()) {
- Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert));
+ Converts.push_back(DAG.getNode(IA64ISD::GETFD, dl,
+ MVT::i64, ValToConvert));
}
}
// Emit all stores, make sure they occur before any copies into physregs.
if (!Stores.empty())
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
+ Chain = DAG.getNode(ISD::TokenFactor, dl,
+ MVT::Other, &Stores[0],Stores.size());
static const unsigned IntArgRegs[] = {
IA64::out0, IA64::out1, IA64::out2, IA64::out3,
@@ -477,7 +481,7 @@
assert(0 && "this should never happen!\n");
// to make way for a hack:
- Chain = DAG.getNode(IA64ISD::BRCALL, NodeTys,
+ Chain = DAG.getNode(IA64ISD::BRCALL, dl, NodeTys,
&CallOperands[0], CallOperands.size());
InFlag = Chain.getValue(1);
@@ -508,7 +512,7 @@
InFlag = zeroReg.getValue(2);
Chain = zeroReg.getValue(1);
- RetVal = DAG.getSetCC(MVT::i1, boolInR8, zeroReg, ISD::SETNE);
+ RetVal = DAG.getSetCC(dl, MVT::i1, boolInR8, zeroReg, ISD::SETNE);
break;
}
case MVT::i8:
@@ -520,9 +524,9 @@
// keep track of whether it is sign or zero extended (todo: bools?)
/* XXX
RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
- MVT::i64, RetVal, DAG.getValueType(RetTyVT));
+ dl, MVT::i64, RetVal, DAG.getValueType(RetTyVT));
*/
- RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
+ RetVal = DAG.getNode(ISD::TRUNCATE, dl, RetTyVT, RetVal);
break;
case MVT::i64:
RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
@@ -532,7 +536,7 @@
case MVT::f32:
RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
Chain = RetVal.getValue(1);
- RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal,
+ RetVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, RetVal,
DAG.getIntPtrConstant(0));
break;
case MVT::f64:
diff --git a/lib/Target/IA64/IA64ISelLowering.h b/lib/Target/IA64/IA64ISelLowering.h
index 9b0854f..edf7eb8 100644
--- a/lib/Target/IA64/IA64ISelLowering.h
+++ b/lib/Target/IA64/IA64ISelLowering.h
@@ -54,7 +54,8 @@
/// LowerArguments - This hook must be implemented to indicate how we should
/// lower the arguments for the specified function, into the specified DAG.
virtual void LowerArguments(Function &F, SelectionDAG &DAG,
- SmallVectorImpl<SDValue> &ArgValues);
+ SmallVectorImpl<SDValue> &ArgValues,
+ DebugLoc dl);
/// LowerCallTo - This hook lowers an abstract call to a function into an
/// actual call.
@@ -62,7 +63,8 @@
LowerCallTo(SDValue Chain, const Type *RetTy,
bool RetSExt, bool RetZExt, bool isVarArg, bool isInreg,
unsigned CC, bool isTailCall,
- SDValue Callee, ArgListTy &Args, SelectionDAG &DAG);
+ SDValue Callee, ArgListTy &Args, SelectionDAG &DAG,
+ DebugLoc dl);
/// LowerOperation - for custom lowering specific ops
/// (currently, only "ret void")
diff --git a/lib/Target/PIC16/PIC16ISelLowering.cpp b/lib/Target/PIC16/PIC16ISelLowering.cpp
index 83d7a3e..4e7e1e4 100644
--- a/lib/Target/PIC16/PIC16ISelLowering.cpp
+++ b/lib/Target/PIC16/PIC16ISelLowering.cpp
@@ -172,7 +172,7 @@
PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call,
MVT RetVT, const SDValue *Ops,
unsigned NumOps, bool isSigned,
- SelectionDAG &DAG) {
+ SelectionDAG &DAG, DebugLoc dl) {
TargetLowering::ArgListTy Args;
Args.reserve(NumOps);
@@ -190,7 +190,7 @@
const Type *RetTy = RetVT.getTypeForMVT();
std::pair<SDValue,SDValue> CallInfo =
LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
- false, CallingConv::C, false, Callee, Args, DAG);
+ false, CallingConv::C, false, Callee, Args, DAG, dl);
return CallInfo.first;
}
@@ -758,7 +758,8 @@
SmallVector<SDValue, 2> Ops(2);
Ops[0] = Value;
Ops[1] = Amt;
- SDValue Call = MakePIC16Libcall(CallCode, N->getValueType(0), &Ops[0], 2, true, DAG);
+ SDValue Call = MakePIC16Libcall(CallCode, N->getValueType(0), &Ops[0], 2,
+ true, DAG, N->getDebugLoc());
return Call;
}
diff --git a/lib/Target/PIC16/PIC16ISelLowering.h b/lib/Target/PIC16/PIC16ISelLowering.h
index 78571f4..011d91e 100644
--- a/lib/Target/PIC16/PIC16ISelLowering.h
+++ b/lib/Target/PIC16/PIC16ISelLowering.h
@@ -168,7 +168,7 @@
// Make PIC16 Libcall
SDValue MakePIC16Libcall(PIC16ISD::PIC16Libcall Call, MVT RetVT,
const SDValue *Ops, unsigned NumOps, bool isSigned,
- SelectionDAG &DAG);
+ SelectionDAG &DAG, DebugLoc dl);
// Check if operation has a direct load operand.
inline bool isDirectLoad(const SDValue Op);
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 67c2536..1a192a1 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1229,6 +1229,7 @@
SDValue Trmp = Op.getOperand(1); // trampoline
SDValue FPtr = Op.getOperand(2); // nested function
SDValue Nest = Op.getOperand(3); // 'nest' parameter value
+ DebugLoc dl = Op.getNode()->getDebugLoc();
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = (PtrVT == MVT::i64);
@@ -1254,7 +1255,7 @@
LowerCallTo(Chain, Op.getValueType().getTypeForMVT(), false, false,
false, false, CallingConv::C, false,
DAG.getExternalSymbol("__trampoline_setup", PtrVT),
- Args, DAG);
+ Args, DAG, dl);
SDValue Ops[] =
{ CallResult.first, CallResult.second };
diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp
index b1031b4..af5d6e5 100644
--- a/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/lib/Target/Sparc/SparcISelLowering.cpp
@@ -77,7 +77,8 @@
/// in FP registers for fastcc functions.
void
SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
- SmallVectorImpl<SDValue> &ArgValues) {
+ SmallVectorImpl<SDValue> &ArgValues,
+ DebugLoc dl) {
MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
diff --git a/lib/Target/Sparc/SparcISelLowering.h b/lib/Target/Sparc/SparcISelLowering.h
index a0e3c65..acd1b50 100644
--- a/lib/Target/Sparc/SparcISelLowering.h
+++ b/lib/Target/Sparc/SparcISelLowering.h
@@ -58,7 +58,8 @@
unsigned Depth = 0) const;
virtual void LowerArguments(Function &F, SelectionDAG &DAG,
- SmallVectorImpl<SDValue> &ArgValues);
+ SmallVectorImpl<SDValue> &ArgValues,
+ DebugLoc dl);
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB);
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 2aa2e4a..2c79da5 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -5532,10 +5532,12 @@
Args.push_back(Entry);
Entry.Node = Size;
Args.push_back(Entry);
+ // FIXME provide DebugLoc info
std::pair<SDValue,SDValue> CallResult =
LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
CallingConv::C, false,
- DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG);
+ DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG,
+ DebugLoc::getUnknownLoc());
return CallResult.second;
}