commit 7f484a5fff140ade284a1af34641da067bea11ae
author Misha Brukman <brukman+llvm@gmail.com> Thu Jun 24 23:51:00 2004 +0000
committer Misha Brukman <brukman+llvm@gmail.com> Thu Jun 24 23:51:00 2004 +0000
tree 5a3fb263fa548a435ec9ac34cdc68e81a1afb93e
parent 64aed54684b205c47fda075918150d14ba4193bc

* Lowercase the register names
* Parenthesize assert() expressions correctly
* Fix spacing around for() and if() statements


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14384 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPC32AsmPrinter.cpp

diff --git a/lib/Target/PowerPC/PPC32AsmPrinter.cpp b/lib/Target/PowerPC/PPC32AsmPrinter.cpp
index 7c714ac..ef60584 100644
--- a/lib/Target/PowerPC/PPC32AsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPC32AsmPrinter.cpp
@@ -426,8 +426,8 @@
     }
     // FALLTHROUGH
   case MachineOperand::MO_MachineRegister:
-      O << RI.get(MO.getReg()).Name;
-      return;
+    O << LowercaseString(RI.get(MO.getReg()).Name);
+    return;
 
   case MachineOperand::MO_SignExtendedImmed:
   case MachineOperand::MO_UnextendedImmed:
@@ -511,15 +511,15 @@
   unsigned int ArgCount = Desc.TSFlags & PPC32II::ArgCountMask;
   unsigned int ArgType[5];
 
-  ArgType[0] = (Desc.TSFlags>>PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask;
-  ArgType[1] = (Desc.TSFlags>>PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask;
-  ArgType[2] = (Desc.TSFlags>>PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask;
-  ArgType[3] = (Desc.TSFlags>>PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask;
-  ArgType[4] = (Desc.TSFlags>>PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask;
+  ArgType[0] = (Desc.TSFlags >> PPC32II::Arg0TypeShift) & PPC32II::ArgTypeMask;
+  ArgType[1] = (Desc.TSFlags >> PPC32II::Arg1TypeShift) & PPC32II::ArgTypeMask;
+  ArgType[2] = (Desc.TSFlags >> PPC32II::Arg2TypeShift) & PPC32II::ArgTypeMask;
+  ArgType[3] = (Desc.TSFlags >> PPC32II::Arg3TypeShift) & PPC32II::ArgTypeMask;
+  ArgType[4] = (Desc.TSFlags >> PPC32II::Arg4TypeShift) & PPC32II::ArgTypeMask;
   
-  assert((Desc.TSFlags & PPC32II::VMX == 0) &&
+  assert(((Desc.TSFlags & PPC32II::VMX) == 0) &&
          "Instruction requires VMX support");
-  assert((Desc.TSFlags & PPC32II::PPC64 == 0) &&
+  assert(((Desc.TSFlags & PPC32II::PPC64) == 0) &&
          "Instruction requires 64 bit support");
   //assert ( ValidOpcodes(MI, ArgType) && "Instruction has invalid inputs");
   ++EmittedInsts;
@@ -566,7 +566,7 @@
       printOp(MI->getOperand(2));
     O << ")\n";
   } else {
-    for(i = 0; i< ArgCount; i++) {
+    for (i = 0; i < ArgCount; ++i) {
       if (ArgType[i] == PPC32II::Gpr0 && 
           MI->getOperand(i).getReg() == PPC32::R0)
         O << "0";
@@ -574,7 +574,7 @@
         //std::cout << "DEBUG " << (*(TM.getRegisterInfo())).get(MI->getOperand(i).getReg()).Name << "\n";
         printOp(MI->getOperand(i));
       }
-      if( ArgCount - 1 == i)
+      if (ArgCount - 1 == i)
         O << "\n";
       else
         O << ", ";