Handle 'lshr' instruction with SCEVUDiv object.
Comment the xor %x, -1 case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53167 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Analysis/ScalarEvolution.cpp b/lib/Analysis/ScalarEvolution.cpp
index d615c75..4462986 100644
--- a/lib/Analysis/ScalarEvolution.cpp
+++ b/lib/Analysis/ScalarEvolution.cpp
@@ -1742,12 +1742,14 @@
}
break;
case Instruction::Xor:
- // If the RHS of the xor is a signbit, then this is just an add.
- // Instcombine turns add of signbit into xor as a strength reduction step.
if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
+ // If the RHS of the xor is a signbit, then this is just an add.
+ // Instcombine turns add of signbit into xor as a strength reduction step.
if (CI->getValue().isSignBit())
return SE.getAddExpr(getSCEV(U->getOperand(0)),
getSCEV(U->getOperand(1)));
+
+ // If the RHS of xor is -1, then this is a not operation.
else if (CI->isAllOnesValue())
return SE.getNotSCEV(getSCEV(U->getOperand(0)));
}
@@ -1763,6 +1765,16 @@
}
break;
+ case Instruction::LShr:
+ // Turn logical shift right of a constant into a unsigned divide.
+ if (ConstantInt *SA = dyn_cast<ConstantInt>(U->getOperand(1))) {
+ uint32_t BitWidth = cast<IntegerType>(V->getType())->getBitWidth();
+ Constant *X = ConstantInt::get(
+ APInt(BitWidth, 1).shl(SA->getLimitedValue(BitWidth)));
+ return SE.getUDivExpr(getSCEV(U->getOperand(0)), getSCEV(X));
+ }
+ break;
+
case Instruction::Trunc:
return SE.getTruncateExpr(getSCEV(U->getOperand(0)), U->getType());