Don't require pseudo-instructions to carry encoding information.
For now this is distinct from isCodeGenOnly, as code-gen-only
instructions can (and often do) still have encoding information
associated with them. Once we've migrated all of them over to true
pseudo-instructions that are lowered to real instructions prior to
the printer/emitter, we can remove isCodeGenOnly and just use isPseudo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134539 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/ARMDecoderEmitter.cpp b/utils/TableGen/ARMDecoderEmitter.cpp
index a7cbbcd..8a5dc8b 100644
--- a/utils/TableGen/ARMDecoderEmitter.cpp
+++ b/utils/TableGen/ARMDecoderEmitter.cpp
@@ -421,6 +421,9 @@
protected:
// Populates the insn given the uid.
void insnWithID(insn_t &Insn, unsigned Opcode) const {
+ if (AllInstructions[Opcode]->isPseudo)
+ return;
+
BitsInit &Bits = getBitsField(*AllInstructions[Opcode]->TheDef, "Inst");
for (unsigned i = 0; i < BIT_WIDTH; ++i)
diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp
index 9d4dc5c4..d828dfc 100644
--- a/utils/TableGen/CodeEmitterGen.cpp
+++ b/utils/TableGen/CodeEmitterGen.cpp
@@ -34,7 +34,8 @@
for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
I != E; ++I) {
Record *R = *I;
- if (R->getValueAsString("Namespace") == "TargetOpcode")
+ if (R->getValueAsString("Namespace") == "TargetOpcode" ||
+ R->getValueAsBit("isPseudo"))
continue;
BitsInit *BI = R->getValueAsBitsInit("Inst");
@@ -231,7 +232,8 @@
const CodeGenInstruction *CGI = *IN;
Record *R = CGI->TheDef;
- if (R->getValueAsString("Namespace") == "TargetOpcode") {
+ if (R->getValueAsString("Namespace") == "TargetOpcode" ||
+ R->getValueAsBit("isPseudo")) {
o << " 0U,\n";
continue;
}
@@ -255,7 +257,8 @@
for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
IC != EC; ++IC) {
Record *R = *IC;
- if (R->getValueAsString("Namespace") == "TargetOpcode")
+ if (R->getValueAsString("Namespace") == "TargetOpcode" ||
+ R->getValueAsBit("isPseudo"))
continue;
const std::string &InstName = R->getValueAsString("Namespace") + "::"
+ R->getName();
diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp
index 5fa91be..28b56ba 100644
--- a/utils/TableGen/CodeGenInstruction.cpp
+++ b/utils/TableGen/CodeGenInstruction.cpp
@@ -311,6 +311,7 @@
isAsCheapAsAMove = R->getValueAsBit("isAsCheapAsAMove");
hasExtraSrcRegAllocReq = R->getValueAsBit("hasExtraSrcRegAllocReq");
hasExtraDefRegAllocReq = R->getValueAsBit("hasExtraDefRegAllocReq");
+ isPseudo = R->getValueAsBit("isPseudo");
ImplicitDefs = R->getValueAsListOfDefs("Defs");
ImplicitUses = R->getValueAsListOfDefs("Uses");
diff --git a/utils/TableGen/CodeGenInstruction.h b/utils/TableGen/CodeGenInstruction.h
index 5f1e0be..ad39722 100644
--- a/utils/TableGen/CodeGenInstruction.h
+++ b/utils/TableGen/CodeGenInstruction.h
@@ -235,6 +235,7 @@
bool isAsCheapAsAMove;
bool hasExtraSrcRegAllocReq;
bool hasExtraDefRegAllocReq;
+ bool isPseudo;
CodeGenInstruction(Record *R);
diff --git a/utils/TableGen/EDEmitter.cpp b/utils/TableGen/EDEmitter.cpp
index 4c0d385..9870d91 100644
--- a/utils/TableGen/EDEmitter.cpp
+++ b/utils/TableGen/EDEmitter.cpp
@@ -774,6 +774,11 @@
for (index = 0; index < numInstructions; ++index) {
const CodeGenInstruction& inst = *numberedInstructions[index];
+ // We don't need to do anything for pseudo-instructions, as we'll never
+ // see them here. We'll only see real instructions.
+ if (inst.isPseudo)
+ continue;
+
CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter;
infoArray.addEntry(infoStruct);
diff --git a/utils/TableGen/FixedLenDecoderEmitter.cpp b/utils/TableGen/FixedLenDecoderEmitter.cpp
index ba6cd86..c9dcb01 100644
--- a/utils/TableGen/FixedLenDecoderEmitter.cpp
+++ b/utils/TableGen/FixedLenDecoderEmitter.cpp
@@ -1225,14 +1225,14 @@
//
// This also removes pseudo instructions from considerations of disassembly,
// which is a better design and less fragile than the name matchings.
- BitsInit &Bits = getBitsField(Def, "Inst");
- if (Bits.allInComplete()) return false;
-
// Ignore "asm parser only" instructions.
if (Def.getValueAsBit("isAsmParserOnly") ||
Def.getValueAsBit("isCodeGenOnly"))
return false;
+ BitsInit &Bits = getBitsField(Def, "Inst");
+ if (Bits.allInComplete()) return false;
+
std::vector<OperandInfo> InsnOperands;
// If the instruction has specified a custom decoding hook, use that instead
@@ -1354,7 +1354,8 @@
void FixedLenDecoderEmitter::populateInstructions() {
for (unsigned i = 0, e = NumberedInstructions.size(); i < e; ++i) {
Record *R = NumberedInstructions[i]->TheDef;
- if (R->getValueAsString("Namespace") == "TargetOpcode")
+ if (R->getValueAsString("Namespace") == "TargetOpcode" ||
+ R->getValueAsBit("isPseudo"))
continue;
if (populateInstruction(*NumberedInstructions[i], i))