Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183494 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
index 4bf1e33..0df50e1 100644
--- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp
+++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
@@ -71,8 +71,8 @@
// 3. Handling of the esoteric cases in "Resource-based Instruction Grouping".
//
-PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii)
- : TII(tii) {
+PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetMachine &TM)
+ : TM(TM) {
EndDispatchGroup();
}
@@ -91,7 +91,7 @@
bool &isFirst, bool &isSingle,
bool &isCracked,
bool &isLoad, bool &isStore) {
- const MCInstrDesc &MCID = TII.get(Opcode);
+ const MCInstrDesc &MCID = TM.getInstrInfo()->get(Opcode);
isLoad = MCID.mayLoad();
isStore = MCID.mayStore();