Use the BuildMI overload that sets up a destination register
instead of the one that doesn't and then adding it manually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55006 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index 62fac06..5a7c896 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -70,10 +70,9 @@
const TargetRegisterClass* RC) {
MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetInstrDesc &II = TII->get(MachineInstOpcode);
- MachineInstr *MI = BuildMI(*MF, II);
unsigned ResultReg = MRI.createVirtualRegister(RC);
- MI->addOperand(MachineOperand::CreateReg(ResultReg, true));
+ MachineInstr *MI = BuildMI(*MF, II, ResultReg);
MBB->push_back(MI);
return ResultReg;
@@ -84,10 +83,9 @@
unsigned Op0) {
MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetInstrDesc &II = TII->get(MachineInstOpcode);
- MachineInstr *MI = BuildMI(*MF, II);
unsigned ResultReg = MRI.createVirtualRegister(RC);
- MI->addOperand(MachineOperand::CreateReg(ResultReg, true));
+ MachineInstr *MI = BuildMI(*MF, II, ResultReg);
MI->addOperand(MachineOperand::CreateReg(Op0, false));
MBB->push_back(MI);
@@ -99,10 +97,9 @@
unsigned Op0, unsigned Op1) {
MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetInstrDesc &II = TII->get(MachineInstOpcode);
- MachineInstr *MI = BuildMI(*MF, II);
unsigned ResultReg = MRI.createVirtualRegister(RC);
- MI->addOperand(MachineOperand::CreateReg(ResultReg, true));
+ MachineInstr *MI = BuildMI(*MF, II, ResultReg);
MI->addOperand(MachineOperand::CreateReg(Op0, false));
MI->addOperand(MachineOperand::CreateReg(Op1, false));