If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55840 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/X86/constant-pool-remat-0.ll b/test/CodeGen/X86/constant-pool-remat-0.ll
index 144d442..40caaa6 100644
--- a/test/CodeGen/X86/constant-pool-remat-0.ll
+++ b/test/CodeGen/X86/constant-pool-remat-0.ll
@@ -1,13 +1,13 @@
; RUN: llvm-as < %s | llc -march=x86-64 | grep LCPI | count 3
; RUN: llvm-as < %s | llc -march=x86-64 -stats -info-output-file - | grep asm-printer | grep 6
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep LCPI | count 3
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats -info-output-file - | grep asm-printer | grep 8
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats -info-output-file - | grep asm-printer | grep 12
-declare fastcc float @qux(float %y)
+declare float @qux(float %y)
-define fastcc float @array(float %a) nounwind {
+define float @array(float %a) nounwind {
%n = mul float %a, 9.0
- %m = call fastcc float @qux(float %n)
+ %m = call float @qux(float %n)
%o = mul float %m, 9.0
ret float %o
}