If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55840 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/X86/fastcc-2.ll b/test/CodeGen/X86/fastcc-2.ll
new file mode 100644
index 0000000..40c753e
--- /dev/null
+++ b/test/CodeGen/X86/fastcc-2.ll
@@ -0,0 +1,10 @@
+; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin -mattr=+sse2 | grep movsd
+; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin -mattr=+sse2 | grep mov | count 1
+
+define i32 @foo() nounwind {
+entry:
+ tail call fastcc void @bar( double 1.000000e+00 ) nounwind
+ ret i32 0
+}
+
+declare fastcc void @bar(double)