commit 841d12d9ac489ec33d933af96d77dd4fc2a4cee2
author Chris Lattner <sabre@nondot.org> Tue Oct 18 16:51:22 2005 +0000
committer Chris Lattner <sabre@nondot.org> Tue Oct 18 16:51:22 2005 +0000
tree 0c884d9f0daff7fe80e93c989a4844002feb00bf
parent 076866c50f6b6c45271285eb268b585b00bed9dc

Fix the JIT encoding of LWA, LD, STD, and STDU.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23787 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPCAsmPrinter.cpp

diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index f158913..f2e2396 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -117,6 +117,10 @@
                             MVT::ValueType VT) {
       O << (unsigned short)MI->getOperand(OpNo).getImmedValue();
     }
+    void printS16X4ImmOperand(const MachineInstr *MI, unsigned OpNo,
+                              MVT::ValueType VT) {
+      O << (short)MI->getOperand(OpNo).getImmedValue()*4;
+    }
     void printBranchOperand(const MachineInstr *MI, unsigned OpNo,
                             MVT::ValueType VT) {
       // Branches can take an immediate operand.  This is used by the branch

lib/Target/PowerPC/PPCInstrInfo.td

diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index d18dd6d..ad4444b 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -89,6 +89,9 @@
 def u16imm  : Operand<i32> {
   let PrintMethod = "printU16ImmOperand";
 }
+def s16immX4  : Operand<i32> {   // Multiply imm by 4 before printing.
+  let PrintMethod = "printS16X4ImmOperand";
+}
 def target : Operand<i32> {
   let PrintMethod = "printBranchOperand";
 }
@@ -282,15 +285,15 @@
 // DS-Form instructions.  Load/Store instructions available in PPC-64
 //
 let isLoad = 1 in {
-def LWA  : DSForm_1<58, 2, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
+def LWA  : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
                     "lwa $rT, $DS($rA)">, isPPC64;
-def LD   : DSForm_2<58, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
+def LD   : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
                     "ld $rT, $DS($rA)">, isPPC64;
 }
 let isStore = 1 in {
-def STD  : DSForm_2<62, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
+def STD  : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
                     "std $rT, $DS($rA)">, isPPC64;
-def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
+def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
                     "stdu $rT, $DS($rA)">, isPPC64;
 }
 

lib/Target/PowerPC/PPCRegisterInfo.cpp

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index fe03359..658e294 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -271,6 +271,15 @@
     MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
     MI.SetMachineOperandReg(2, PPC::R0);
   } else {
+    switch (MI.getOpcode()) {
+    case PPC::LWA:
+    case PPC::LD:
+    case PPC::STD:
+    case PPC::STDU:
+      assert((Offset & 3) == 0 && "Invalid frame offset!");
+      Offset >>= 2;    // The actual encoded value has the low two bits zero.
+      break;
+    }
     MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
                               Offset);
   }