Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index f56043f..9b6825d 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -25,7 +25,6 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
-#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/Debug.h"
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 0415e19..4d8a237 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -24,12 +24,13 @@
#include "llvm/Constants.h"
#include "llvm/Instruction.h"
#include "llvm/Intrinsics.h"
+#include "llvm/GlobalValue.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/VectorExtras.h"
#include "llvm/Support/MathExtras.h"
@@ -685,16 +686,16 @@
Op.getValue(1), Sign);
}
Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand());
- if (DAG.getMachineFunction().liveout_empty())
- DAG.getMachineFunction().addLiveOut(ARM::R0);
+ if (DAG.getMachineFunction().getRegInfo().liveout_empty())
+ DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
break;
case 5:
Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
// If we haven't noted the R0+R1 are live out, do so now.
- if (DAG.getMachineFunction().liveout_empty()) {
- DAG.getMachineFunction().addLiveOut(ARM::R0);
- DAG.getMachineFunction().addLiveOut(ARM::R1);
+ if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
+ DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
+ DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1);
}
break;
}
@@ -917,7 +918,7 @@
MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
SDOperand Root = Op.getOperand(0);
std::vector<SDOperand> ArgValues;
- SSARegMap *RegMap = MF.getSSARegMap();
+ MachineRegisterInfo &RegInfo = MF.getRegInfo();
static const unsigned GPRArgRegs[] = {
ARM::R0, ARM::R1, ARM::R2, ARM::R3
@@ -935,20 +936,20 @@
SDOperand ArgValue;
if (ObjGPRs == 1) {
- unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
- MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
+ unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
+ RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
vRegs[NumGPRs] = VReg;
ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
if (ObjectVT == MVT::f32)
ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
} else if (ObjGPRs == 2) {
- unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
- MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
+ unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
+ RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
vRegs[NumGPRs] = VReg;
ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
- VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
- MF.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
+ VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
+ RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
vRegs[NumGPRs+1] = VReg;
SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
@@ -1002,7 +1003,7 @@
};
MachineFunction &MF = DAG.getMachineFunction();
- SSARegMap *RegMap = MF.getSSARegMap();
+ MachineRegisterInfo &RegInfo = MF.getRegInfo();
MachineFrameInfo *MFI = MF.getFrameInfo();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
@@ -1019,8 +1020,8 @@
SmallVector<SDOperand, 4> MemOps;
for (; NumGPRs < 4; ++NumGPRs) {
- unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
- MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
+ unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
+ RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
MemOps.push_back(Store);
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 979410a..8328cef 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -24,6 +24,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLocation.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
@@ -1206,14 +1207,14 @@
for (unsigned i = 0; CSRegs[i]; ++i) {
unsigned Reg = CSRegs[i];
bool Spilled = false;
- if (MF.isPhysRegUsed(Reg)) {
+ if (MF.getRegInfo().isPhysRegUsed(Reg)) {
AFI->setCSRegisterIsSpilled(Reg);
Spilled = true;
CanEliminateFrame = false;
} else {
// Check alias registers too.
for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
- if (MF.isPhysRegUsed(*Aliases)) {
+ if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
Spilled = true;
CanEliminateFrame = false;
}
@@ -1286,7 +1287,7 @@
// If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
// Spill LR as well so we can fold BX_RET to the registers restore (LDM).
if (!LRSpilled && CS1Spilled) {
- MF.setPhysRegUsed(ARM::LR);
+ MF.getRegInfo().setPhysRegUsed(ARM::LR);
AFI->setCSRegisterIsSpilled(ARM::LR);
NumGPRSpills++;
UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
@@ -1298,7 +1299,7 @@
// Darwin ABI requires FP to point to the stack slot that contains the
// previous FP.
if (STI.isTargetDarwin() || hasFP(MF)) {
- MF.setPhysRegUsed(FramePtr);
+ MF.getRegInfo().setPhysRegUsed(FramePtr);
NumGPRSpills++;
}
@@ -1312,7 +1313,7 @@
unsigned Reg = UnspilledCS1GPRs[i];
// Don't spiil high register if the function is thumb
if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) {
- MF.setPhysRegUsed(Reg);
+ MF.getRegInfo().setPhysRegUsed(Reg);
AFI->setCSRegisterIsSpilled(Reg);
if (!isReservedReg(MF, Reg))
ExtraCSSpill = true;
@@ -1322,7 +1323,7 @@
} else if (!UnspilledCS2GPRs.empty() &&
!AFI->isThumbFunction()) {
unsigned Reg = UnspilledCS2GPRs.front();
- MF.setPhysRegUsed(Reg);
+ MF.getRegInfo().setPhysRegUsed(Reg);
AFI->setCSRegisterIsSpilled(Reg);
if (!isReservedReg(MF, Reg))
ExtraCSSpill = true;
@@ -1378,7 +1379,7 @@
}
if (Extras.size() && NumExtras == 0) {
for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
- MF.setPhysRegUsed(Extras[i]);
+ MF.getRegInfo().setPhysRegUsed(Extras[i]);
AFI->setCSRegisterIsSpilled(Extras[i]);
}
} else {
@@ -1392,7 +1393,7 @@
}
if (ForceLRSpill) {
- MF.setPhysRegUsed(ARM::LR);
+ MF.getRegInfo().setPhysRegUsed(ARM::LR);
AFI->setCSRegisterIsSpilled(ARM::LR);
AFI->setLRIsSpilledForFarJump(true);
}
@@ -1446,9 +1447,9 @@
if (isThumb) {
// Check if R3 is live in. It might have to be used as a scratch register.
- for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end();
- I != E; ++I) {
- if ((*I).first == ARM::R3) {
+ for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
+ E = MF.getRegInfo().livein_end(); I != E; ++I) {
+ if (I->first == ARM::R3) {
AFI->setR3IsLiveIn(true);
break;
}