commit 85e6815d83d2b0027b5197aa17b5f32074bc9a8e
author Dan Gohman <gohman@apple.com> Wed Jul 09 20:12:26 2008 +0000
committer Dan Gohman <gohman@apple.com> Wed Jul 09 20:12:26 2008 +0000
tree 553b3d6706c33cb3ee6acb66c6d4a86f52d419e4
parent 9a06ed93594d7a1894d4e61c2925a98f661dd221

Reuse the MO variable instead of recomputing it in RegAllocLocal.
Keep RegAllocSimple in sync.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53351 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/RegAllocSimple.cpp

diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index ce4b420..9ad3840 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -188,12 +188,12 @@
 
     // Loop over uses, move from memory into registers.
     for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
-      MachineOperand &op = MI->getOperand(i);
+      MachineOperand &MO = MI->getOperand(i);
 
-      if (op.isRegister() && op.getReg() &&
-          TargetRegisterInfo::isVirtualRegister(op.getReg())) {
-        unsigned virtualReg = (unsigned) op.getReg();
-        DOUT << "op: " << op << "\n";
+      if (MO.isRegister() && MO.getReg() &&
+          TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
+        unsigned virtualReg = (unsigned) MO.getReg();
+        DOUT << "op: " << MO << "\n";
         DOUT << "\t inst[" << i << "]: ";
         DEBUG(MI->print(*cerr.stream(), TM));
 
@@ -201,7 +201,7 @@
         // register in any given instruction
         unsigned physReg = Virt2PhysRegMap[virtualReg];
         if (physReg == 0) {
-          if (op.isDef()) {
+          if (MO.isDef()) {
             int TiedOp = Desc.findTiedToSrcOperand(i);
             if (TiedOp == -1) {
               physReg = getFreeReg(virtualReg);
@@ -222,8 +222,8 @@
             Virt2PhysRegMap[virtualReg] = physReg;
           }
         }
-        MI->getOperand(i).setReg(physReg);
-        DOUT << "virt: " << virtualReg << ", phys: " << op.getReg() << "\n";
+        MO.setReg(physReg);
+        DOUT << "virt: " << virtualReg << ", phys: " << MO.getReg() << "\n";
       }
     }
     RegClassIdx.clear();