64-bit atomic operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49949 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h
index d9ced1b..bd13baf 100644
--- a/lib/Target/PowerPC/PPCISelLowering.h
+++ b/lib/Target/PowerPC/PPCISelLowering.h
@@ -152,13 +152,13 @@
/// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
MTFSF,
- /// LWARX = This corresponds to PPC lwarx instrcution: load word and
+ /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
/// reserve indexed. This is used to implement atomic operations.
- LWARX,
+ LARX,
- /// STWCX = This corresponds to PPC stwcx. instrcution: store word
- /// conditional indexed. This is used to implement atomic operations.
- STWCX,
+ /// STCX = This corresponds to PPC stcx. instrcution: store conditional
+ /// indexed. This is used to implement atomic operations.
+ STCX,
/// CMP_UNRESERVE = Test for equality and "unreserve" if not true. This
/// is used to implement atomic operations.