commit 860e7cdab9d5eceda5ac52ae0ddfb4bdab0067f2
author Patrik Hagglund <patrik.h.hagglund@ericsson.com> Thu Dec 13 18:45:35 2012 +0000
committer Patrik Hagglund <patrik.h.hagglund@ericsson.com> Thu Dec 13 18:45:35 2012 +0000
tree cc0de031414033493f26e82345b6d77ba0a8b0d4
parent d14baf450b17d47c80950b59e3dd8844b79821f7

Change TargetLowering::getRepRegClassFor to take an MVT, instead of
EVT.

Accordingly, change RegDefIter to contain MVTs instead of EVTs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170140 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/MachineLICM.cpp

diff --git a/lib/CodeGen/MachineLICM.cpp b/lib/CodeGen/MachineLICM.cpp
index 8c2b4e6..760cf8a 100644
--- a/lib/CodeGen/MachineLICM.cpp
+++ b/lib/CodeGen/MachineLICM.cpp
@@ -780,7 +780,7 @@
                                        unsigned Reg, unsigned OpIdx,
                                        unsigned &RCId, unsigned &RCCost) const {
   const TargetRegisterClass *RC = MRI->getRegClass(Reg);
-  EVT VT = *RC->vt_begin();
+  MVT VT = *RC->vt_begin();
   if (VT == MVT::Untyped) {
     RCId = RC->getID();
     RCCost = 1;